JPS57118641A - Lifting-off method - Google Patents

Lifting-off method

Info

Publication number
JPS57118641A
JPS57118641A JP529081A JP529081A JPS57118641A JP S57118641 A JPS57118641 A JP S57118641A JP 529081 A JP529081 A JP 529081A JP 529081 A JP529081 A JP 529081A JP S57118641 A JPS57118641 A JP S57118641A
Authority
JP
Japan
Prior art keywords
spacer
layer
photoresist layer
photoresist
exposed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP529081A
Other languages
Japanese (ja)
Inventor
Kenji Mitsui
Toru Okuma
Morio Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp, Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electronics Corp
Priority to JP529081A priority Critical patent/JPS57118641A/en
Publication of JPS57118641A publication Critical patent/JPS57118641A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Abstract

PURPOSE:To make the formation of a fine pattern such as precision wiring possible by a method wherein two layers of photoresist is used as the spacer of the lifting-off method. CONSTITUTION:After the first photoresist layer 8 is formed on the silicone dioxide film 2 on the surface of a silicone substrate 1, the layer is exposed using the specfied masking pattern, then the second photoresist layer 10 is formed and exposed using the masking pattern of smaller width. After that, by developing process, spacer like a eaves is formed over the aperture. When Al layer is formed, it is divided into 12 and 13 by the spacer, so that electrode wiring 13 can be formed by removing the photoresist layer.
JP529081A 1981-01-16 1981-01-16 Lifting-off method Pending JPS57118641A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP529081A JPS57118641A (en) 1981-01-16 1981-01-16 Lifting-off method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP529081A JPS57118641A (en) 1981-01-16 1981-01-16 Lifting-off method

Publications (1)

Publication Number Publication Date
JPS57118641A true JPS57118641A (en) 1982-07-23

Family

ID=11607103

Family Applications (1)

Application Number Title Priority Date Filing Date
JP529081A Pending JPS57118641A (en) 1981-01-16 1981-01-16 Lifting-off method

Country Status (1)

Country Link
JP (1) JPS57118641A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107331601A (en) * 2017-06-29 2017-11-07 苏州苏纳光电有限公司 The photoresist deposition and method for stripping metal of double exposure
CN110379707A (en) * 2019-08-21 2019-10-25 无锡英菲感知技术有限公司 A kind of lift-off structure of metal patternization and preparation method thereof

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51129190A (en) * 1975-05-02 1976-11-10 Fujitsu Ltd Manufacturing method of semiconductor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51129190A (en) * 1975-05-02 1976-11-10 Fujitsu Ltd Manufacturing method of semiconductor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107331601A (en) * 2017-06-29 2017-11-07 苏州苏纳光电有限公司 The photoresist deposition and method for stripping metal of double exposure
CN110379707A (en) * 2019-08-21 2019-10-25 无锡英菲感知技术有限公司 A kind of lift-off structure of metal patternization and preparation method thereof

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