JPS57192044A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS57192044A JPS57192044A JP7654481A JP7654481A JPS57192044A JP S57192044 A JPS57192044 A JP S57192044A JP 7654481 A JP7654481 A JP 7654481A JP 7654481 A JP7654481 A JP 7654481A JP S57192044 A JPS57192044 A JP S57192044A
- Authority
- JP
- Japan
- Prior art keywords
- region
- gate
- fets
- type
- floating gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
PURPOSE:To minimize characteristic variation and to perform accurate measurement, by forming first and second semiconductor regions on a semiconductor substrate, providing a double junction structure for a P-N junction, and connecting a floating gate on the second region. CONSTITUTION:At the position adjacent to a CMOS, another P<+> type well 14 whose depth and impurity concentration are the same a those of a P<+> type well 3 is formed. In these wells, N<+> type regions 4 and 5 and an N<+> type diffused region 15 are formed. The region 15 and polysilicon electrodes 16, 17... for FETs are connected by a wiring 18. Meanwhile, the floating gate 19 which is common to the FETs is provided. Since the gate 19 is connected to the region 15 formed in the region 14 in the substate, the charge which is to be stored in the gate is discharged from the region 15 to the substrate, the variation in characteristics such as threshold voltage is minimized, and the characteristic control in manufacturing the device based on the measurement can be normally performed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7654481A JPS57192044A (en) | 1981-05-22 | 1981-05-22 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7654481A JPS57192044A (en) | 1981-05-22 | 1981-05-22 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS57192044A true JPS57192044A (en) | 1982-11-26 |
Family
ID=13608202
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7654481A Pending JPS57192044A (en) | 1981-05-22 | 1981-05-22 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57192044A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6570212B1 (en) * | 2000-05-24 | 2003-05-27 | Lattice Semiconductor Corporation | Complementary avalanche injection EEPROM cell |
| CN100392837C (en) * | 2003-05-23 | 2008-06-04 | 上海宏力半导体制造有限公司 | Testing structure for testing acupoint bag implanting result |
-
1981
- 1981-05-22 JP JP7654481A patent/JPS57192044A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6570212B1 (en) * | 2000-05-24 | 2003-05-27 | Lattice Semiconductor Corporation | Complementary avalanche injection EEPROM cell |
| CN100392837C (en) * | 2003-05-23 | 2008-06-04 | 上海宏力半导体制造有限公司 | Testing structure for testing acupoint bag implanting result |
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