GB1519995A - Semiconductor devices - Google Patents

Semiconductor devices

Info

Publication number
GB1519995A
GB1519995A GB37389/75A GB3738975A GB1519995A GB 1519995 A GB1519995 A GB 1519995A GB 37389/75 A GB37389/75 A GB 37389/75A GB 3738975 A GB3738975 A GB 3738975A GB 1519995 A GB1519995 A GB 1519995A
Authority
GB
United Kingdom
Prior art keywords
drain
layer
source regions
type
depletion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB37389/75A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of GB1519995A publication Critical patent/GB1519995A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
    • G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

1519995 Semiconductor devices HITACHI Ltd 11 Sept 1975 [11 Sept 1974] 37389/75 Heading H1K In a semiconductor device, in particular a Read only memory integrated circuit, depletion and enhancement type IGFETS QD 1 &c., and QE, &c., respectively, are formed at the intersections of drain, source regions 2 with bands of polycrystalline silicon gate electrodes 5 so as to produce a matrix configuration as shown in Fig. 5. As shown, a relatively shallow P-type depletion channel 3<SP>1</SP> is produced by an ionimplantation of boron through a twin layer 4 of SiO 2 formed on an N-type substrate 1. After forming the bands of polycrystalline gate electrodes 5, the source and drain regions 2 are introduced through windows in the layer 4. Alternatively, a deep P-type depletion layer (3), Fig. 6a (not shown) is produced by thermal diffusion. The IGFETS QD 1 .... forming a channel even at zero gate voltage, are normally in "on" state, and thereby the drain and source regions of the QD 1 ... IFGETS are electrically connected, thus obviating the need for prior at aluminium wiring shocking the drain and source regions at certain matrix points.
GB37389/75A 1974-09-11 1975-09-11 Semiconductor devices Expired GB1519995A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP49103927A JPS5947464B2 (en) 1974-09-11 1974-09-11 semiconductor equipment

Publications (1)

Publication Number Publication Date
GB1519995A true GB1519995A (en) 1978-08-02

Family

ID=14367051

Family Applications (1)

Application Number Title Priority Date Filing Date
GB37389/75A Expired GB1519995A (en) 1974-09-11 1975-09-11 Semiconductor devices

Country Status (5)

Country Link
JP (1) JPS5947464B2 (en)
DE (1) DE2540350B2 (en)
GB (1) GB1519995A (en)
HK (1) HK35281A (en)
MY (1) MY8200018A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2471083A1 (en) * 1979-11-30 1981-06-12 Dassault Electronique Integrated MOSFET code circuit for e.g. bank card - receives cryptic code and has function of transistors determined by doping to prevent analysis
EP0042420A1 (en) * 1979-12-28 1981-12-30 Western Electric Co Method for fabricating igfet integrated circuits.

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4080718A (en) * 1976-12-14 1978-03-28 Smc Standard Microsystems Corporation Method of modifying electrical characteristics of MOS devices using ion implantation
FR2398386A1 (en) * 1977-07-18 1979-02-16 Mostek Corp METHOD AND STRUCTURE FOR CROSSING INFORMATION SIGNALS IN AN INTEGRATED CIRCUIT DEVICE
JPS6028144B2 (en) * 1983-08-24 1985-07-03 株式会社日立製作所 Manufacturing method of MIS type semiconductor device
JPS6028145B2 (en) * 1983-08-24 1985-07-03 株式会社日立製作所 Manufacturing method of MIS type semiconductor device
JPS6133013A (en) * 1984-07-25 1986-02-15 Nec Corp Ring oscillator
JPH0783062B2 (en) * 1985-06-18 1995-09-06 株式会社東芝 Master-slice type semiconductor device
FR2716586B1 (en) * 1994-02-23 1996-04-05 Bull Sa Door-or-Exclusive integrated in a III-V semiconductor.

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS559417B2 (en) * 1971-10-09 1980-03-10
JPS5232557B2 (en) * 1972-03-14 1977-08-22
JPS4924330A (en) * 1972-06-28 1974-03-04

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2471083A1 (en) * 1979-11-30 1981-06-12 Dassault Electronique Integrated MOSFET code circuit for e.g. bank card - receives cryptic code and has function of transistors determined by doping to prevent analysis
EP0042420A1 (en) * 1979-12-28 1981-12-30 Western Electric Co Method for fabricating igfet integrated circuits.
EP0042420A4 (en) * 1979-12-28 1984-11-22 Western Electric Co Method for fabricating igfet integrated circuits.

Also Published As

Publication number Publication date
JPS5947464B2 (en) 1984-11-19
HK35281A (en) 1981-07-31
DE2540350A1 (en) 1976-04-01
DE2540350B2 (en) 1980-07-03
JPS5131180A (en) 1976-03-17
MY8200018A (en) 1982-12-31

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PE20 Patent expired after termination of 20 years

Effective date: 19950910