JPS5522887A - Mis type field effect semiconductor device - Google Patents

Mis type field effect semiconductor device

Info

Publication number
JPS5522887A
JPS5522887A JP10884378A JP10884378A JPS5522887A JP S5522887 A JPS5522887 A JP S5522887A JP 10884378 A JP10884378 A JP 10884378A JP 10884378 A JP10884378 A JP 10884378A JP S5522887 A JPS5522887 A JP S5522887A
Authority
JP
Japan
Prior art keywords
layer
sio
laminated
successively
parasitic capacitance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10884378A
Other languages
Japanese (ja)
Other versions
JPS5755305B2 (en
Inventor
Shunpei Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Corp
Original Assignee
TDK Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TDK Corp filed Critical TDK Corp
Priority to JP10884378A priority Critical patent/JPS5522887A/en
Publication of JPS5522887A publication Critical patent/JPS5522887A/en
Publication of JPS5755305B2 publication Critical patent/JPS5755305B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Element Separation (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: To eliminate a parasitic capacitance due to a PN junction by prodividing the circumference and bottom face of a source and drain layer adjacent to a field odidization layer buried.
CONSTITUTION: A field oxidization film 2 is provided in a p-type Si substarate having an n-type bury layer 24 provided therein, an n epitaxial-layer is layer is laminated to from a field oxidization film 23 selectively. Successively, an SiO26, Si3N47 and SiO28 are laminated to prevent a charge transfer between a gate film 6 and Si3N47. Successively, a p-type Si 9 is laminated, a Mo is covered, and a gate 15, lead 11 and capacity 36 are formed by a selective etching. According to such a construction, the occurrence of a parasitic capacitance due to a pn-junction can be prevented. Successively, an SiO216 is covered, an opening is selectively provided, and an Al electrode 18 is formed. This MISFET divece has a less parasitic capacitance, therefore, being very excellent in a superhigh frequency characteristic.
COPYRIGHT: (C)1980,JPO&Japio
JP10884378A 1978-09-05 1978-09-05 Mis type field effect semiconductor device Granted JPS5522887A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10884378A JPS5522887A (en) 1978-09-05 1978-09-05 Mis type field effect semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10884378A JPS5522887A (en) 1978-09-05 1978-09-05 Mis type field effect semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP3062571A Division JPS5624385B1 (en) 1971-05-07 1971-05-07

Publications (2)

Publication Number Publication Date
JPS5522887A true JPS5522887A (en) 1980-02-18
JPS5755305B2 JPS5755305B2 (en) 1982-11-24

Family

ID=14494976

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10884378A Granted JPS5522887A (en) 1978-09-05 1978-09-05 Mis type field effect semiconductor device

Country Status (1)

Country Link
JP (1) JPS5522887A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS587869A (en) * 1981-07-07 1983-01-17 Nec Corp Semiconductor device
JPS5831574A (en) * 1981-08-19 1983-02-24 Toshiba Corp Semiconductor device and manufacture thereof
WO2001018873A1 (en) * 1999-09-09 2001-03-15 Infineon Technologies Ag Mos transistor and method for producing the same
US11251577B2 (en) 2017-03-14 2022-02-15 Sw Automatisierung Gmbh Arrangement apparatus for receiving and arranging wire sections

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4940115A (en) * 1972-08-16 1974-04-15

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4940115A (en) * 1972-08-16 1974-04-15

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS587869A (en) * 1981-07-07 1983-01-17 Nec Corp Semiconductor device
JPS5831574A (en) * 1981-08-19 1983-02-24 Toshiba Corp Semiconductor device and manufacture thereof
WO2001018873A1 (en) * 1999-09-09 2001-03-15 Infineon Technologies Ag Mos transistor and method for producing the same
US6563179B2 (en) 1999-09-09 2003-05-13 Infineon Technologies MOS transistor and method for producing the transistor
US11251577B2 (en) 2017-03-14 2022-02-15 Sw Automatisierung Gmbh Arrangement apparatus for receiving and arranging wire sections

Also Published As

Publication number Publication date
JPS5755305B2 (en) 1982-11-24

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