JPS6473674A - Mos-type field-effect transistor - Google Patents

Abstract

PURPOSE:To reduce dependence of a capacitance value in a depletion layer on a voltage by a method wherein a buried layer of one conductivity type is formed in a substrate under an island region and a depth of this buried layer is formed in a position where an expansion of the depletion layer extended from the island region reaches this buried layer at an island potential during an operation. CONSTITUTION:This transistor is constituted by containing a P<+> type buried layer 2, a P- type epitaxial layer 3, an N<+> type source diffusion region 4, an N+ type island diffusion region 5 and an N<+> type drain diffusion region 6 on a P-type semiconductor substrate 1. In addition, a first gate electrode 10 and a second electrode 11 are contained on a gate oxide film 13. In addition, a source electrode 9 and a drain electrode 12 are formed on the source region 4 and the drain 6, respectively. If a distance 8 between the island 5 and the buried region 2 is always set to be shorter than a distance of a depletion layer 7 of a P-N junction during an operation, the depletion layer 7 always reaches the buried layer 2 and is set in a so-called reach-through state. Accordingly, the depletion layer 7 is not expanded beyond the distance 8; a capacitance value CIS does not depend on a voltage.