GB1429696A - - Google Patents

Info

Publication number
GB1429696A
GB1429696A GB4475173A GB4475173A GB1429696A GB 1429696 A GB1429696 A GB 1429696A GB 4475173 A GB4475173 A GB 4475173A GB 4475173 A GB4475173 A GB 4475173A GB 1429696 A GB1429696 A GB 1429696A
Authority
GB
United Kingdom
Prior art keywords
region
substrate
epitaxial layer
type
insulation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB4475173A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of GB1429696A publication Critical patent/GB1429696A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0805—Capacitors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
    • H01L27/0647—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. vertical bipolar transistor and bipolar lateral transistor and resistor
    • H01L27/0652—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
    • H01L27/0658—Vertical bipolar transistor in combination with resistors or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

1429696 Integrated circuits SONY CORP 24 Sept 1973 [25 Sept 1972] 44751/73 Heading H1K In an integrated circuit comprising an MIS structure which includes a diffusion-isolated region of an epitaxial layer formed on a semi-conductor substrate, a highly doped buried region of the same conductivity type as the substrate is provided below the isolated region to increase the Q-factor of the stray capacitance formed by the substrate-epitaxial layer junction. In the Si device shown, an N-type epitaxial layer 2 is grown on a surface of a P-type substrate 1 having a P+ region 20 therein extending to the said surface, and is then divided into mutually isolated regions 10, 17, 21 by a diffused grid-like P-type region 19 which contacts the now buried region 20, a contact 23 on region 19 being, in use, connected to earth or other reference potential. A buried N+ region 101 is is provided beneath region 10. In subsequent diffusion and insulation- and metal-deposition steps, an MIS capacitor 7 is formed in region 21 and a bipolar transistor 11 is formed in region 10; the collector electrode 14 of which is extended to form a bonding pad 15 which, together with underlying insulation 16 and region 17, forms a further MIS structure 18. Insulation layers 4, 16 are single or multiple layers of SiO 2 , Al 2 O 3 , and/or Si 3 N 4 . Bonding pad 15 may be of Al.
GB4475173A 1972-09-25 1973-09-24 Expired GB1429696A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9600772A JPS521877B2 (en) 1972-09-25 1972-09-25

Publications (1)

Publication Number Publication Date
GB1429696A true GB1429696A (en) 1976-03-24

Family

ID=14153103

Family Applications (1)

Application Number Title Priority Date Filing Date
GB4475173A Expired GB1429696A (en) 1972-09-25 1973-09-24

Country Status (7)

Country Link
JP (1) JPS521877B2 (en)
CA (1) CA1004780A (en)
DE (1) DE2348262A1 (en)
FR (1) FR2200636B1 (en)
GB (1) GB1429696A (en)
IT (1) IT994322B (en)
NL (1) NL184814C (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5994450A (en) * 1982-11-19 1984-05-31 Nec Kyushu Ltd Semiconductor device
US5177587A (en) * 1989-07-21 1993-01-05 Linear Technology Corporation Push-back junction isolation semiconductor structure and method
JP5497298B2 (en) * 2009-01-16 2014-05-21 久光製薬株式会社 Sheet patch
JP5974978B2 (en) 2013-05-29 2016-08-23 信越半導体株式会社 Silicon single crystal manufacturing method

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1539873B2 (en) * 1966-10-18 1971-03-11 Deutsche Itt Industries Gmbh, 7800 Freiburg TRANSISTOR
US3544863A (en) * 1968-10-29 1970-12-01 Motorola Inc Monolithic integrated circuit substructure with epitaxial decoupling capacitance
FR2036530A5 (en) * 1969-03-24 1970-12-24 Radiotechnique Compelec

Also Published As

Publication number Publication date
CA1004780A (en) 1977-02-01
JPS521877B2 (en) 1977-01-18
IT994322B (en) 1975-10-20
NL7313221A (en) 1974-03-27
FR2200636B1 (en) 1978-06-30
FR2200636A1 (en) 1974-04-19
JPS4953386A (en) 1974-05-23
NL184814C (en) 1989-11-01
NL184814B (en) 1989-06-01
DE2348262A1 (en) 1974-04-18

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Legal Events

Date Code Title Description
PS Patent sealed
PE20 Patent expired after termination of 20 years

Effective date: 19930923