GB1048424A - Improvements in or relating to semiconductor devices - Google Patents

Improvements in or relating to semiconductor devices

Info

Publication number
GB1048424A
GB1048424A GB3405663A GB3405663A GB1048424A GB 1048424 A GB1048424 A GB 1048424A GB 3405663 A GB3405663 A GB 3405663A GB 3405663 A GB3405663 A GB 3405663A GB 1048424 A GB1048424 A GB 1048424A
Authority
GB
United Kingdom
Prior art keywords
layer
junction
type
inclusion
windows
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB3405663A
Inventor
Fritz Gunter Adam
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Standard Electric Corp
Original Assignee
International Standard Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Standard Electric Corp filed Critical International Standard Electric Corp
Priority to GB3405663A priority Critical patent/GB1048424A/en
Priority to DE1964ST022582 priority patent/DE1292759B/en
Publication of GB1048424A publication Critical patent/GB1048424A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

1,048,424. Semi-conductor devices. INTERNATIONAL STANDARD ELECTRIC CORPORATION. Aug. 28, 1963, No. 34056/63. Addition to 1,007,936. Heading H1K. In a planar semi-conductor device comprising a zone of one conductivity type formed as an inclusion in the surface of a layer of uniform resistivity material of the opposite conductivity type the layer and its junction with the inclusion are insulation covered. A deposited metal electrode making contact with the inclusion extends across the junction over the insulation, which is made thinner where the junction surfaces than it is beyond this point. The thickness at the junction is chosen to provide optimum protection while the thickening elsewhere enables the parasitic capacitance between the electrode and the layer to be reduced. Capacitance may be further reduced by providing outside the junction beneath the insulation a zone making a PN junction with the layer, as in Fig. 2 (not shown). The transistor shown in Fig. 1 is produced in multiple by first providing an N-type layer on a lower resistivity N-type silicon wafer with an oxide layer 10, 2-10 Á thick, and forming windows therein by photolithographic techniques. The surface of the layer is again oxidized to a thickness of 0À5-1 Á within the windows. Apertures are then formed within the windows and boron diffused through them to form P-type base zones 2 in the layer. By a similar technique of phosphorus diffusion N-type emitter zones 3 are formed. Layers 4 and 5 are then partially exposed by removal of oxide and extended base and emitter contacts 8, 9 provided by vapour deposition of aluminium. The wafer is then subdivided and individual transistors mounted on collector headers. If germanium or gallium arsenide is used instead of silicon the oxide layers are provided by vapour deposition.
GB3405663A 1963-08-28 1963-08-28 Improvements in or relating to semiconductor devices Expired GB1048424A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
GB3405663A GB1048424A (en) 1963-08-28 1963-08-28 Improvements in or relating to semiconductor devices
DE1964ST022582 DE1292759B (en) 1963-08-28 1964-08-25 Method for producing a feed line to a diffused semiconductor zone

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB3405663A GB1048424A (en) 1963-08-28 1963-08-28 Improvements in or relating to semiconductor devices

Publications (1)

Publication Number Publication Date
GB1048424A true GB1048424A (en) 1966-11-16

Family

ID=10360824

Family Applications (1)

Application Number Title Priority Date Filing Date
GB3405663A Expired GB1048424A (en) 1963-08-28 1963-08-28 Improvements in or relating to semiconductor devices

Country Status (2)

Country Link
DE (1) DE1292759B (en)
GB (1) GB1048424A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2196476A (en) * 1986-10-14 1988-04-27 Emi Plc Thorn A method for manufacturing a component and a component produced by the method

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3741880A (en) * 1969-10-25 1973-06-26 Nippon Electric Co Method of forming electrical connections in a semiconductor integrated circuit
JPS5232234B2 (en) * 1971-10-11 1977-08-19
US4040891A (en) * 1976-06-30 1977-08-09 Ibm Corporation Etching process utilizing the same positive photoresist layer for two etching steps

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL204955A (en) * 1956-02-28
US2890395A (en) * 1957-10-31 1959-06-09 Jay W Lathrop Semiconductor construction
US2981877A (en) * 1959-07-30 1961-04-25 Fairchild Semiconductor Semiconductor device-and-lead structure
FR1318391A (en) * 1961-04-26 1963-02-15 Clevite Corp Semiconductor device assembly
FR1333007A (en) * 1962-02-16 1963-07-19 Intermetall Method of manufacturing high frequency transistors and transistors conforming to those thus obtained

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2196476A (en) * 1986-10-14 1988-04-27 Emi Plc Thorn A method for manufacturing a component and a component produced by the method
GB2196476B (en) * 1986-10-14 1990-02-14 Emi Plc Thorn A method for manufacturing a component and a component produced by the method

Also Published As

Publication number Publication date
DE1292759B (en) 1969-04-17

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