JPS5598844A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS5598844A
JPS5598844A JP670279A JP670279A JPS5598844A JP S5598844 A JPS5598844 A JP S5598844A JP 670279 A JP670279 A JP 670279A JP 670279 A JP670279 A JP 670279A JP S5598844 A JPS5598844 A JP S5598844A
Authority
JP
Japan
Prior art keywords
layer
type
region
diffused
field effect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP670279A
Other languages
Japanese (ja)
Inventor
Masao Taguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP670279A priority Critical patent/JPS5598844A/en
Publication of JPS5598844A publication Critical patent/JPS5598844A/en
Pending legal-status Critical Current

Links

Landscapes

  • Bipolar Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: To readily fabricate and improve the integrating degree of a semiconductor itegrated circuit by adding further one layer on the p-type and n-type layers of a field effect semiconsuctor element when forming field effect and bipolar transistors on the same substrate.
CONSTITUTION: A p-type layer is epitaxially grown on an n-type silicon substrate 11 to provide an isolating SiO2 film 14 reaching the substrate 11, thereby isolating the p-type layer into the layer 13a of a field effect transistor and the layer 13b of a bipolar transistor. When a p+-type region 15a is newly diffused in one end of the layer 13a so that the layer 13a is in floated state, the variation of the threshold voltage of a channel 12a provided later is prevented, and a p+-type base contact region 15b is formed in the end of the layer 13b. Thereafter, an n-type channel region 12a is diffused in the layer 13a, n+-type regions 5 and 6 are provided in the region 12a, and a gate electrode 3 is formed through a gate oxide film 7 on the region 12a disposed between the regions 5 and 6. An n-type channel region 12b is also diffused in the layer 13b, an n+-type region 16 is provided in the region 12b.
COPYRIGHT: (C)1980,JPO&Japio
JP670279A 1979-01-22 1979-01-22 Semiconductor integrated circuit Pending JPS5598844A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP670279A JPS5598844A (en) 1979-01-22 1979-01-22 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP670279A JPS5598844A (en) 1979-01-22 1979-01-22 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS5598844A true JPS5598844A (en) 1980-07-28

Family

ID=11645642

Family Applications (1)

Application Number Title Priority Date Filing Date
JP670279A Pending JPS5598844A (en) 1979-01-22 1979-01-22 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS5598844A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02244616A (en) * 1989-03-16 1990-09-28 Mitsubishi Electric Corp Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02244616A (en) * 1989-03-16 1990-09-28 Mitsubishi Electric Corp Manufacture of semiconductor device

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