JPS5947464B2 - semiconductor equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated gate field effect transistor (MISFE).
Semiconductor devices using T), especially large-scale integrated circuits (LSI)
Regarding.

Semiconductor devices in the information processing field are required to have a high degree of integration in order to improve reliability and reduce costs.

An effective method for meeting this requirement is an LSI in which a MISFET is used as a basic element and each element is integrated on a single semiconductor substrate. In other words, MISLSI, which is configured with MISFET as the basic element, does not require isolation between elements and has a structure that improves the degree of integration by that amount.
The device configuration according to the above has the advantage that the manufacturing yield D can be improved even though it is easy in terms of manufacturing technology.

However, in the multilayer wiring technology that is essential for conventional MISLSI, when electrically interconnecting the electrodes of each MISLSI element, aluminum wiring is used, and the aluminum wiring and the electrodes of each of the above elements are connected to each other. When connecting a contact hole, even if the contact hole is formed using precise mask alignment and fine photoresist technology, the area occupied by the contact hole will be large due to the mask dimensional accuracy, which will reduce the integration density of MISLSI. had the disadvantage of decreasing. For example, the conventional insulated gate 9-mode
5 Only memory (MISROM) is roughly constructed from a path array as shown in FIG.

The pattern of this MISROM formed on one semiconductor substrate is shown in FIGS. 2 and 3. In Fig. 1, Q, ~Q, is an enhancement type MlsFE.
'R, A, ~A3 are address wirings, and B, ~B3 are output signal wirings. Further, FIG. 3 is a cross-sectional view of the cut plane shown by the dashed line in FIG.
In the figure and FIG. 3, 1 is an N-type silicon substrate, 2 and 3 are P'-type regions which are source or drain regions, and 4
5 is an insulating film, 5 is a polycrystalline silicon layer for silicon gate, 6 is
is an aluminum wiring, and T is a contact hole that electrically connects the aluminum wiring and the P” type region for drain.As is clear from Figure 1 and Figure 3, multiple enhancement type MISFETs are used and In order to connect the drain P″t″ type region of each MISFET to the ground line, a MISROM configured by connecting the MISFETs in parallel must use aluminum wiring as a multilayer wiring. P
It is necessary to form a contact hole on the P' type region for the drain of each MISFET in order to electrically connect it to the P' type region.

Moreover, a MISROM configured with a memo9 array as shown in FIG. To increase. Therefore, an extremely large number of contact holes are required to connect the above-mentioned multilayer wiring using aluminum wiring and the P-type region for drain, which reduces the degree of integration of MISLSI including conventional MISROM. There were flaws. Therefore, it is an object of the present invention to
An object of the present invention is to provide a semiconductor device in which ETs can be placed on a semiconductor substrate at extremely high density.

In order to achieve such an object of the present invention, according to the basic structure of the present invention, in an insulated gate read-only memory comprising a plurality of insulated gate field effect elements formed in a matrix on a semiconductor substrate, The plurality of insulated gate field effect elements are connected in series in each column, and
Gate electrodes of the insulated gate field effect devices located in each row are formed by wiring layers extending across each column so as to be commonly connected to each other. Each of the insulated gate field effect elements is defined as either a depletion type or an enhancement type according to the stored information in the 9-de-on 9- memo 9-, and the depletion type and the enhancement type are defined. It is characterized in that it shows two different pieces of memory information depending on the difference in information.

This will be explained in detail below using examples.

FIG. 4 shows an MI which is a semiconductor device which is an embodiment of the present invention.
This is a schematic diagram showing part of a complicated electric circuit in which a MISROM is incorporated into an SLSI, and Fig. 5 is a front view of the electric circuit formed on a single silicon board.
, FIG. 6 is a schematic cross-sectional view of FIG. 5 indicated by a dashed line, taken from the XX' direction. In Figures 4 to 6, A1 to A3 are address wirings, B, to B3 are output signal wirings, and QE to QE5 are enhancement type M
ISFET NQDI-Ql is a 9-deep type MISFET. In addition, in Figures 5 and 6, 1
is an N-type silicon substrate, 2 is P for source or drain
``F type region, 3 is depth 9 type MISFET
4 is an insulating film, and 5 is a polycrystalline silicon layer for a silicon gate.6 Now, as shown in FIG. 4, a plurality of MISFETs are arranged in a matrix, and QE, to Q
Let E5 be an enhancement type MISFET, and Q
By using 9-deep type MISFETs for D and QD4), an extremely highly integrated MISROM can be constructed on a single semiconductor substrate.

That is, the MISROM in this embodiment is MISR
Enhancement type P that operates like an OM bit.
Channel MISFET (When the gate voltage is 0V, a channel is not formed and the source and drain are in a cut-off state, and then a channel is formed only when a certain threshold voltage is applied to the gate electrode, and the source and drain are in a conductive state.) (a so-called normally off-type element) and a depletion type P element in which the surface of the N-type silicon substrate under the gate electrode is made into a Pf type by thermal diffusion or ion implantation.
Since it is composed of a channel MISFET (a so-called normally-on type element in which a channel is formed even when the gate voltage is 0 V and the source and drain are in a conductive state), it is a depletion type P-channel MISFET. is always in the on state.1 On the other hand, the enhancement type P channel MlSFET has two states, an on state and an off state.

Therefore, it is possible to distinguish between ゞ1″ and ′o′2, and when addressed, an output signal current is obtained where the enhancement type MISFET is connected, and the MISR
Able to perform OM operations. That is, the operation of the ROM of this embodiment is as follows.

Whether or not the MISROM stores information (for example, "1") is distinguished depending on whether the MISFETs arranged in a matrix are of the enhancement type.

For example, if you want to write "1"" at the intersection of a matrix,
The MISFET at the intersection is defined as an enforcement type, and conversely, if it is desired to write "0''" in a matrix intersection, the MISFET at that intersection is defined as a depletion type. In Figure 4, output signal wiring B,
If you look at QDl (depression type)
, QEl (enhancement type) and QE, (enhancement type) respectively store the ゛゛0''゛, ゛1''' and ゛F'. Similarly, if we look at output signal wiring B, QO2, QO
, hexagram and QF:3 respectively store "0-"0"" and "F". M like this
In ISROM, a read operation is performed as follows. When reading out whether a given MISFET is ``0'''' or ``1'''', the MISFET
0M, that is, a level that turns off the enhancement type MISFET, is supplied only to the address wiring to which T is connected, and to the remaining two address wirings,
A level that turns on the enhancement type MISFET (this voltage level is defined as -V (.(V)) is supplied.

For example, when detecting the storage state of a depletion type P-channel MISFET QO, which is connected in series to the output signal wiring B1, the address wiring A is selected, and a 0V signal is applied to the selected address wiring A1. (H
MISFET QDl is always on regardless of the high level).

This is because the MISFET QOl is of the depletion type as described above. On the other hand, the unselected MISFETs QO, QO2 are turned on by one signal (LOW level) applied by the unselected address wires A2, A,.

Therefore, all MISFETQOl,QE,,Q
Since E2 is on, a current path occurs in the series circuit made up of these MISFETs. If a current path occurs in the series circuit like this, MISFET QOl is 0''''
It can be determined that the person remembers the On the other hand, when detecting the storage state of the enhancement type MISFET QEl, the address wiring A2 is selected, and a 0V signal (high level) is applied to the selected address wiring A2, thereby turning off the MISFET QEl.

This is because the MISFET QEl is of the enhancement type as described above. At this time, A
-V for 1 trigram and A3. (LOW level), both MISFET QOl and QE2 are turned on. Therefore, MISFETQOl,QEl,QE
A series circuit consisting of two selected MISFETQOl
is off, so no current path occurs. Therefore,
Since no current path occurs in the series circuit, in this case, the MIS
Contrary to the above, it can be determined that FETQEl stores "1".In the above manner, a certain MISFE
A selection signal is applied to the gate of T, and the output signal level is determined depending on whether or not there is a current path at that time, and the selected MISFET accordingly stores ``0'' or ``''. It is possible to read out whether the

Furthermore, the MISROM of this embodiment includes a depletion type MISFET and an enhancement type MISFET.
Since the FETs are arranged in rows and columns, there is no need to use aluminum wiring as a multilayer wiring, and moreover, the p+ type region 2, which is the source or drain region, and the polycrystalline silicon 5, which is the silicon gate electrode, intersect with each other. There is no need for multi-layer wiring even where there is.

Furthermore, in the MISROM of this embodiment, the p+ type region for the drain of each MISFET is connected to the p+ type region for the source adjacent to the p+ type region for the source.
Since the connection is made through the +-type region, it is possible to omit the conventional method of providing a b1 contact hole in which the drain is connected to the ground line and connecting it to the aluminum wiring as a multilayer wiring. Therefore, the MISROM of this embodiment is an extremely highly integrated MISLSI b1, and since the manufacturing method is simple and easy, the manufacturing yield b is improved and the MISLSI is highly reliable.

As is clear from the embodiments described above, the present invention provides a MISLSI with a circuit configuration in which a polycrystalline silicon layer for a silicon gate and a P+ type region for a source or drain intersect.
can be easily constructed without using multilayer wiring, and therefore a MISLSI with an extremely high degree of integration can be obtained. The present invention is not limited to the above-mentioned embodiments, but
It can be applied to various types of semiconductor devices.

The present invention also provides an enhancement type MISFET.
Since depletion type MISFETs are appropriately arranged in matrix on one semiconductor substrate, the semiconductor device has an extremely high degree of integration and can be formed using a simple and easy manufacturing technique.

[Brief explanation of drawings]

Figure 1 is a schematic layout diagram of a conventional MISROM used as one of the configuration blocks of MISLSI, and Figures 2 and 3 show the pattern of a conventional MISROM formed on a single semiconductor substrate. The figures shown in FIGS. 4 to 6 are schematic diagrams showing one embodiment of the present invention. 1... N-type silicon substrate, 2, 3...
P+ type region, 4... Insulating film, 5... Polycrystalline silicon layer, 6... Aluminum wiring, 7
...Contact hole, A,,A,,A3...
...Address wiring, B,, B2, B3...
Output signal wiring, Ql, Q,, Q3, Q4, Q,...
...Enhancement type MISFETlQOl
, QO2, QO3, QO4... Depression type MISFET ~ QE! , Q? ,QE3,QE
4, QE5゜゜゜・・・Enhancement type MI
SFETlX, X5......Symbols at both ends of the cutting line.

Claims (1)

[Claims] 1. An insulated gate type lead-only device consisting of a plurality of insulated gate field effect elements formed in a matrix on a semiconductor substrate.
In the memory, the plurality of insulated gate field effect devices are connected in series in each column, and the gate electrodes of the insulated gate field effect devices located in each row are connected horizontally across each column so that they are commonly connected to each other. Each of the plurality of insulated gate field effect elements arranged in rows and columns is formed by cutting and extending wiring layers, and each of the plurality of insulated gate field effect elements is of a depletion type or an enhancement type according to the information stored in the read-only memory. stipulated in either
This insulated gate type read-only memory is characterized by being able to indicate two different kinds of stored information depending on the difference between the depletion type and the enhancement type. 2. The insulated gate read-only memory according to claim 1, wherein the wiring layer is made of a polycrystalline silicon layer. 3. The selected channel region operating as the depletion type insulated gate field effect device comprises a region of the opposite conductivity type to the semiconductor substrate formed by ion implantation. The insulated gate read-only memory described in item 1.