DE2540350B2 - Semiconductor circuit with a matrix of insulating film field effect transistors - Google Patents

Description

A semiconductor circuit of the type specified in the preamble of claim 1 is from German Offenlegungsschrift 23 12 413 known. there becomes part of the insulating-layer field-effect transistors produced during the production of the matrix leave the given matrix crossing points, while the remaining transistors with the help of also short-circuited diffusion areas introduced into the substrate in the course of production so that no field effect transistor is formed at these points.

As a result of these short circuits, there is a risk of malfunction in the case of the known circuit Patterns of the logical control. Such a malfunction can occur when the supply voltage via one of the short circuits mentioned to a transistor that is not actually activated arrives there from its source or drain electrode on its gate and turns it on, which can occasionally cause all of the transistors of a matrix line become conductive even though they are not activated. In such a case, the with the output terminal connected to this row will generate an incorrect signal.

The invention is based on the object of a semiconductor circuit of the type specified at the beginning to be designed in such a way that with the same circuit complexity and the same space requirements, the tendency to Disturbance behavior is reduced.

The inventive solution to this problem is specified in the characterizing part of claim 1. The subsequently provided VerarniHngs field effect transistors represent at the relevant point of the respective "> matrix line a resistance corresponding to the doping of the depletion channel, which hinders a further coupling of the supply voltage to the transistors connected in the same line. Rather, part of the supply potential is over

ίο the effective capacitance between the source * or drain electrode and the gate electrode of the depletion field effect transistor as a result of the resistance of the depletion zone is derived basically the same function reduces the risk of incorrect behavior
From "IBM Technical Disclosure Bulletin", Volume 16, No. 5 (October 1973), pages 1530 and 1531, it is known per se to integrate enhancement and depletion field effect transistors in a common substrate. However, there is no indication in the publication of using a combination of these two types of field effect transistors in a matrix circuit of the type specified at the outset for solving the above-mentioned object.

Advantageous further developments of the invention are characterized in the subclaims

An embodiment of the invention is given below Explained in more detail with reference to the drawing In the drawing shows

F i g. 1 is a schematic circuit diagram for a section of a read-only memory matrix, the MIS field effect transistors used

F i g. 2 is a schematic plan view of a similar matrix circuit and FIG

F i g. 3a and 3b cross-sectional views along the line IH-III in Figure 2 to explain two different Refinements.

In the drawings, the reference symbols A \ -Aj indicate address wirings, B \ -b \ wirings for the output signals, Qe \ - Qes MISFETs of the enhancement type and Qd \ - Qd * MISFETs of the processing

mung type. In F ί g. 2 and 3, numeral 1 indicates an N-type silicon substrate, numeral 2 denotes a P ⁺ region for source or drain, numerals 3 or 3 'denotes a P region for a channel in the MISFET of the depletion type, numeral 4 denotes a

^{Vi indicates an} insulating layer and the reference numeral 5 indicates a polycrystalline silicon layer for the gate.

Cin MIS-ROM (read-only memory made of MIS field effect transistors) with a very high integration density can thereby be fabricated on a single semiconductor substrate

"that the plurality of individual MISFETs are arranged in a matrix form, as shown in Fig. 1, and that the field effect transistors Qe \ -Qe5 MISFETs of the enhancement type, and the field effect transistors Qd \ -Qd * MISFETs of the United States

armor type are

In this embodiment, the MIS-ROM consists of MISFETs of the enhancement type, which the bits of the Process MIS-ROM, as well as from the MISFET's of the depletion type, whereby the surface of the silicon substrate

'' 'N-type strats under the gate electrodes by thermal diffusion or by ion implantation to the P + type is made. The enrichment-type MISFETs are elements that are normally "switched off"

tet «where at a gate voltage of zero no channel is formed and the connection between source and drain is not conductive Threshold voltage applied to the gate electrode, the channel is formed and the connection between source and drain put into the conductive state. The mentioned MISFET's of the depletion type are on the other hand elements that are normally "switched on", for which a Gate voltage of zero volts forms the channel and the connection between source and drain is conductive The depletion type MISFETs are always "on" while the Enrichment type MISFETs have two states, namely the "switched on" and the "switched off" Condition. Therefore the logical binary values "1" and "0" can be distinguished, and the MIS-ROM can be operated so that at a position where an enhancement type MISFET if there is an output signal current is generated when this point is addressed

If the polycrystalline layers are used as gate electrodes and connecting layers, it is much more advantageous to create thin or flat channel layers 3 'of the MOSFETs of the depletion type (see FIG. 3b) by ion implantation of foreign atoms, for example boron, than to produce thick or deep channel layers 3 (see Fig.3a) by thermal diffusion of boron. Such MOSFET matrix is prepared by a thin SiOrScnicht of a thickness of 50 nm is formed on the surface region of the silicon substrate of N-type to 120 on which the MOSFET is to be formed, boron ions partially _r through the thin SiO layer penetrate into the substrate to form P-type channel regions for the depletion-type transistors. Thereafter, polycrystalline silicon wirings are formed on the thin SiO2 layer by applying silicon and the thin SiO2 layer is partially removed in order to form openings for the source and drain regions of the MOSFET. Then P-type foreign atoms, for example boron atoms, are released through the openings in

ίο diffused or introduced the substrate surface, the silicon wiring serving as a diffusion mask. Thus, a MOSFET of the depletion or enhancement type is formed at each intersection area at which the semiconductor areas of the input wirings 5 made of polycrystalline silicon and the output wirings 2 of the P + type intersect, with all MOSFETs having thin gate insulation layers essentially have the same thickness of 50 to 150 nm as in FIG. 3b. Since the MIS-ROM contains the MISFET's vcct depletion type and enhancement type in matrix form, it is not necessary to use aluminum wiring as multilayer wiring, nor is it necessary to use multilayer wiring itself when the source and drain regions 2 and the silicon gate electrodes 5 form intersections. In the MIS-ROM of this embodiment, since the P + -type drain region of each MISFET is connected to the adjacent P + -type source region via the

jo P + range is connected it does not require the To connect the collector to the earth line or the aluminum wiring as multi-layer wiring, where contact holes must be provided.

1 sheet of drawings

Claims (5)

Claims; 1. Semiconductor circuit with a matrix of insulating-layer field effect transistors integrated in a common semiconductor substrate, the source-drain paths of the transistors in the same row being connected in series to an output terminal, while the gate electrodes of all transistors in a column are each connected to an address input, characterized in that a transistor (Qd ι to Qd *, Qb \ to Qes) is provided at each crossing point of the matrix rows and columns that a part of these transistors (Qe \ to Qes) enrichment -Field effect transistors and the remaining transistors (Q _D \ to Qd *) are depletion field effect transistors. 2. A circuit according to claim 1, characterized in that the impurity concentration of the channel regions (3 ,, S) of the depletion field effect transistors (Qd \ to Qd *) is lower than that of the source and drain regions (2). 3. A circuit according to claim 1 or 2, characterized in that the depth of the channel regions (3 ') of the depletion field effect transistors (Qd ι to Qd *) is less than that of the source and drain regions (2). 4. A circuit according to claim 3, characterized in that the channel regions (3 ') of the depletion field effect transistors (Qd ι to Qd *) are generated by ion implantation of foreign atoms. 5. Circuit after ad? ^r Claims 1 to 4, characterized in that the gate electrodes (5) of all transistors consist of aK> polycrystalline silicon.