JPS57180177A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS57180177A
JPS57180177A JP56065901A JP6590181A JPS57180177A JP S57180177 A JPS57180177 A JP S57180177A JP 56065901 A JP56065901 A JP 56065901A JP 6590181 A JP6590181 A JP 6590181A JP S57180177 A JPS57180177 A JP S57180177A
Authority
JP
Japan
Prior art keywords
island
polycrystalline
covered
implanted
ions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56065901A
Other languages
Japanese (ja)
Inventor
Shinji Onga
Kenji Taniguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56065901A priority Critical patent/JPS57180177A/en
Publication of JPS57180177A publication Critical patent/JPS57180177A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain a circuit device with an excellent characteristic and high integration by a method wherein a polycrystalline Si using MOSFET is provided with a gate electrode on its top and bottom surfaces. CONSTITUTION:A p type Si substrate 1 is provided with n<+> layers 21 and 22 covered with an SiO2 film 3, then is covered with selectively, successively formed polycrystalline Si island 41 and 42. The island 41 (for enhancement type device Q1) is implanted with B ions while the island 42 (for depletion type device Q2) is implanted with As ions. Polycrystalline Si layers 61 and 62 are placed on thermally oxidized films 51 and 52. Next, sources 71 and 72 and drains 81 and 82 are built by As doping, which are in turn covered by an insulator film 9. Providing of a wiring 10 completes an E/D type MOS inverter. The driver Q1 gates are made in a common connection into a signal input end and the load Q2 gate is made in a common connection with the Q1 drain and Q2 source into a signal output end. In an inverter of this structure, the output voltage delay behind the input is extremely small in length and the output wave contains few spikes, which result in an excellent switching characteristic and high integration.
JP56065901A 1981-04-30 1981-04-30 Semiconductor device Pending JPS57180177A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56065901A JPS57180177A (en) 1981-04-30 1981-04-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56065901A JPS57180177A (en) 1981-04-30 1981-04-30 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS57180177A true JPS57180177A (en) 1982-11-06

Family

ID=13300323

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56065901A Pending JPS57180177A (en) 1981-04-30 1981-04-30 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS57180177A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6215853A (en) * 1985-07-15 1987-01-24 Nec Corp Semiconductor device
JPH02211668A (en) * 1989-02-11 1990-08-22 Takehide Shirato Semiconductor device
US5677550A (en) * 1992-04-15 1997-10-14 British Technology Group Limited Integrated circuit devices including insulated-gate transistor device having two separately biasable gates
JP2015039018A (en) * 2014-10-07 2015-02-26 株式会社半導体エネルギー研究所 Semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6215853A (en) * 1985-07-15 1987-01-24 Nec Corp Semiconductor device
JPH02211668A (en) * 1989-02-11 1990-08-22 Takehide Shirato Semiconductor device
US5677550A (en) * 1992-04-15 1997-10-14 British Technology Group Limited Integrated circuit devices including insulated-gate transistor device having two separately biasable gates
JP2015039018A (en) * 2014-10-07 2015-02-26 株式会社半導体エネルギー研究所 Semiconductor device

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