JPS5572082A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5572082A
JPS5572082A JP14748278A JP14748278A JPS5572082A JP S5572082 A JPS5572082 A JP S5572082A JP 14748278 A JP14748278 A JP 14748278A JP 14748278 A JP14748278 A JP 14748278A JP S5572082 A JPS5572082 A JP S5572082A
Authority
JP
Japan
Prior art keywords
gate
transistor
type
terminal
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14748278A
Other languages
Japanese (ja)
Inventor
Kokichi Sawada
Heihachi Matsumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP14748278A priority Critical patent/JPS5572082A/en
Publication of JPS5572082A publication Critical patent/JPS5572082A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To obtain a multi-input gate circuit with a less occupation area per gate circuit by making the driver transistor alone as a multi-layer construction in a gate circuit of a MOS semiconductor device.
CONSTITUTION: An n-type drain region 2 and an n-type source region 3 are formed by diffusion on a p-type Si substrate 4 to produce a channel region 5 comprising an n-type inversion layer therebetween. Then, on the channel region, a gate insulating layer 6 having two gate electrodes 1a and 1b buried is provided to make an n channel 2 layer gate transistor. In such a manner, a load transistor 11 and a driver transistor 12 are formed on one substrate and connected in series. The connection point of the transistors is connected to an output terminal while the other ends of the transistors each to the power source terminal 9 and the ground terminal 10. In addition, the first gate or the transistor 12 is connected to the input terminal 7a while the second gate thereof to the input terminal 7b.
COPYRIGHT: (C)1980,JPO&Japio
JP14748278A 1978-11-25 1978-11-25 Semiconductor device Pending JPS5572082A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14748278A JPS5572082A (en) 1978-11-25 1978-11-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14748278A JPS5572082A (en) 1978-11-25 1978-11-25 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5572082A true JPS5572082A (en) 1980-05-30

Family

ID=15431385

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14748278A Pending JPS5572082A (en) 1978-11-25 1978-11-25 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5572082A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5646428A (en) * 1994-07-05 1997-07-08 Sanyo Electric Co., Ltd. Output circuit provided with source follower circuit having depletion type MOS transistor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5646428A (en) * 1994-07-05 1997-07-08 Sanyo Electric Co., Ltd. Output circuit provided with source follower circuit having depletion type MOS transistor
US5912483A (en) * 1994-07-05 1999-06-15 Sanyo Electric Company, Ltd. Output circuit provided with source follower circuit having depletion type MOS transistor

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