JPS5794984A - Semiconductor storage device - Google Patents
Semiconductor storage deviceInfo
- Publication number
- JPS5794984A JPS5794984A JP17075580A JP17075580A JPS5794984A JP S5794984 A JPS5794984 A JP S5794984A JP 17075580 A JP17075580 A JP 17075580A JP 17075580 A JP17075580 A JP 17075580A JP S5794984 A JPS5794984 A JP S5794984A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- load
- circuit
- storage device
- igfet6
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Read Only Memory (AREA)
Abstract
PURPOSE:To reduce the size of a load IGFET by using a field effect transistor (IGFET) of a load insulating gate type as a constant-current load. CONSTITUTION:A bias circuit 5 biasing the gate electrode of a load IGFET1 to a saturation region is formed by connecting a P channel bias setting IGFET6 whose gate and drain are connected together and a diffused resistance 7 with high impedance in series. Then, the potential of the drain elecrode of the IGFET6, obtained by the bias circuit 5, is supplied to the gate elecrode of each IGFET1 of a semiconductor storage device. Therefore, the FET1 is held at a gate potential automatically by the circuit 5 and the need for an auxiliary power source is eliminated to reduce the size of every FET1 by adding one circuit 5.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55170755A JPS5936357B2 (en) | 1980-12-02 | 1980-12-02 | semiconductor storage device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55170755A JPS5936357B2 (en) | 1980-12-02 | 1980-12-02 | semiconductor storage device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5794984A true JPS5794984A (en) | 1982-06-12 |
JPS5936357B2 JPS5936357B2 (en) | 1984-09-03 |
Family
ID=15910780
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55170755A Expired JPS5936357B2 (en) | 1980-12-02 | 1980-12-02 | semiconductor storage device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5936357B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0449218A2 (en) * | 1990-03-29 | 1991-10-02 | Nec Corporation | Semiconductor memory device having signal receiving facility fabricated from BI-CMOS circuits |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03113411U (en) * | 1990-02-28 | 1991-11-20 |
-
1980
- 1980-12-02 JP JP55170755A patent/JPS5936357B2/en not_active Expired
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0449218A2 (en) * | 1990-03-29 | 1991-10-02 | Nec Corporation | Semiconductor memory device having signal receiving facility fabricated from BI-CMOS circuits |
Also Published As
Publication number | Publication date |
---|---|
JPS5936357B2 (en) | 1984-09-03 |
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