JPS5619660A - Complementary mis logic circuit - Google Patents
Complementary mis logic circuitInfo
- Publication number
- JPS5619660A JPS5619660A JP9535479A JP9535479A JPS5619660A JP S5619660 A JPS5619660 A JP S5619660A JP 9535479 A JP9535479 A JP 9535479A JP 9535479 A JP9535479 A JP 9535479A JP S5619660 A JPS5619660 A JP S5619660A
- Authority
- JP
- Japan
- Prior art keywords
- region
- layer
- type
- channel
- logic circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000000295 complement effect Effects 0.000 title 1
- 238000000034 method Methods 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- 239000004020 conductor Substances 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 abstract 1
- 230000010354 integration Effects 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Logic Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
PURPOSE:To enhance the integration and to reduce the consuming electric power of the MIS transistors constituting the logic circuit by a method wherein a part of the semiconductor regions and the insulating layers of two MIS transistors are held in common. CONSTITUTION:A P-type region 33 and a P<+>-type region 34 are formed respectively in an N-type Si substrate 31 by diffusion, and an N<+>-type region 35 is provided in the region 33. Extending from the surface of a region 36 in the substrare 31 locating between the regions 33 and 34 to the surface of a region 37 in the neighboring region 33, these surfaces are covered with a united common insulating film 38, and a conductor layer 39 is formed on it. Constituting the circuit in this way, an N-channel type MIS transistor Q3 having the substrate 31 as the source, the region 35 as the drain, the region 37 as the channel, the layer 38 as the gate insulating layer and the layer 39 as the gate electrode layer, is constituted. A P-channel type MIS transistor Q4 having the region 33 as the source, the region 34 as the drain, the region 36 as the channel, the layer 38 as the insulating layer, the layer 39 as the gate electrode layer, is constituted and these transistors Q3 and Q4 are connected in the ordinary method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54095354A JPS5937585B2 (en) | 1979-07-26 | 1979-07-26 | Complementary MIS logic circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54095354A JPS5937585B2 (en) | 1979-07-26 | 1979-07-26 | Complementary MIS logic circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5619660A true JPS5619660A (en) | 1981-02-24 |
JPS5937585B2 JPS5937585B2 (en) | 1984-09-11 |
Family
ID=14135314
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP54095354A Expired JPS5937585B2 (en) | 1979-07-26 | 1979-07-26 | Complementary MIS logic circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5937585B2 (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57190423A (en) * | 1981-05-19 | 1982-11-24 | Toshiba Corp | Semiconductor circuit |
JPS598431A (en) * | 1982-07-07 | 1984-01-17 | Hitachi Ltd | Buffer circuit |
JPS62150749U (en) * | 1986-03-14 | 1987-09-24 | ||
JPS63131366A (en) * | 1986-11-20 | 1988-06-03 | Csk Corp | Card reader |
US5192393A (en) * | 1989-05-24 | 1993-03-09 | Hitachi, Ltd. | Method for growing thin film by beam deposition and apparatus for practicing the same |
US5469085A (en) * | 1991-01-12 | 1995-11-21 | Shibata; Tadashi | Source follower using two pairs of NMOS and PMOS transistors |
US5594372A (en) * | 1989-06-02 | 1997-01-14 | Shibata; Tadashi | Source follower using NMOS and PMOS transistors |
-
1979
- 1979-07-26 JP JP54095354A patent/JPS5937585B2/en not_active Expired
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57190423A (en) * | 1981-05-19 | 1982-11-24 | Toshiba Corp | Semiconductor circuit |
JPH029459B2 (en) * | 1981-05-19 | 1990-03-02 | Tokyo Shibaura Electric Co | |
JPS598431A (en) * | 1982-07-07 | 1984-01-17 | Hitachi Ltd | Buffer circuit |
JPH0440893B2 (en) * | 1982-07-07 | 1992-07-06 | Hitachi Ltd | |
JPS62150749U (en) * | 1986-03-14 | 1987-09-24 | ||
JPS63131366A (en) * | 1986-11-20 | 1988-06-03 | Csk Corp | Card reader |
US5192393A (en) * | 1989-05-24 | 1993-03-09 | Hitachi, Ltd. | Method for growing thin film by beam deposition and apparatus for practicing the same |
US5594372A (en) * | 1989-06-02 | 1997-01-14 | Shibata; Tadashi | Source follower using NMOS and PMOS transistors |
US5469085A (en) * | 1991-01-12 | 1995-11-21 | Shibata; Tadashi | Source follower using two pairs of NMOS and PMOS transistors |
Also Published As
Publication number | Publication date |
---|---|
JPS5937585B2 (en) | 1984-09-11 |
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