JPS5627969A - Mos semiconductor device - Google Patents

Mos semiconductor device

Info

Publication number
JPS5627969A
JPS5627969A JP10399579A JP10399579A JPS5627969A JP S5627969 A JPS5627969 A JP S5627969A JP 10399579 A JP10399579 A JP 10399579A JP 10399579 A JP10399579 A JP 10399579A JP S5627969 A JPS5627969 A JP S5627969A
Authority
JP
Japan
Prior art keywords
source
channel length
contact
semiconductor device
surge input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10399579A
Other languages
Japanese (ja)
Other versions
JPS6313350B2 (en
Inventor
Tatsu Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP10399579A priority Critical patent/JPS5627969A/en
Publication of JPS5627969A publication Critical patent/JPS5627969A/en
Publication of JPS6313350B2 publication Critical patent/JPS6313350B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices

Abstract

PURPOSE:To prevent electrostatic breakdown of the MOS semiconductor device owing to surging input by increasing the channel length at the portion where a current concentration feasibly occurs at the nearest portion to the surge input. CONSTITUTION:A source and a drain diffused layers 2 and 3 formed in an Si substrate 1. An aluminum wire 7 making contact with the source layer 2 is connected to a ground side, and an aluminum wire 8 making contact with the drain layer 3 is connected to an output side. The channel length l' of a part of a gate becoming a surge input side is formed larger than the channel length of other portion. The source contact is partly omitted in a portion 9 where the source interposed between two gates is reduced in width narrower, an interval between the source and the contact of the surge input side is increased to limit the current through a resistor R disposed therebetween .
JP10399579A 1979-08-17 1979-08-17 Mos semiconductor device Granted JPS5627969A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10399579A JPS5627969A (en) 1979-08-17 1979-08-17 Mos semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10399579A JPS5627969A (en) 1979-08-17 1979-08-17 Mos semiconductor device

Publications (2)

Publication Number Publication Date
JPS5627969A true JPS5627969A (en) 1981-03-18
JPS6313350B2 JPS6313350B2 (en) 1988-03-25

Family

ID=14368871

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10399579A Granted JPS5627969A (en) 1979-08-17 1979-08-17 Mos semiconductor device

Country Status (1)

Country Link
JP (1) JPS5627969A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5990958A (en) * 1982-11-16 1984-05-25 Nec Corp Semiconductor device
EP0162460A2 (en) * 1984-05-22 1985-11-27 Nec Corporation Integrated circuit with an input protective device
US6504216B1 (en) * 2000-04-19 2003-01-07 United Microelectronics Corp. Electrostatic discharge protective circuit
JP2007294939A (en) * 2006-03-31 2007-11-08 Oki Electric Ind Co Ltd Semiconductor device
JP2015141993A (en) * 2014-01-28 2015-08-03 ルネサスエレクトロニクス株式会社 semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5990958A (en) * 1982-11-16 1984-05-25 Nec Corp Semiconductor device
EP0162460A2 (en) * 1984-05-22 1985-11-27 Nec Corporation Integrated circuit with an input protective device
US6504216B1 (en) * 2000-04-19 2003-01-07 United Microelectronics Corp. Electrostatic discharge protective circuit
JP2007294939A (en) * 2006-03-31 2007-11-08 Oki Electric Ind Co Ltd Semiconductor device
JP2015141993A (en) * 2014-01-28 2015-08-03 ルネサスエレクトロニクス株式会社 semiconductor device

Also Published As

Publication number Publication date
JPS6313350B2 (en) 1988-03-25

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