JPS62287643A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the crosstalk between interconnections in elements of a semiconductor device from occuring by a method wherein an impurity added layer is provided immediately below an interconnection channel region to be connected to a power supply. CONSTITUTION:An impurity added layer 20 is formed on the surface of a substrate 2 immediately below an interconnection channel region 16 to fix the potential of layer 20 by a power supply Vcc or Vss. A part of layer 20 is protruded sideways to be communicated with a source S2 of an active region 14 for fixing to the ground potential. In such a constitution, the N<+>type layer 20 though increasing the capacity between substrates 2 for interconnections 10, reversely decreases the capacity between the interconnections 10 so that any crosstalk between adjoining interconnections due to higher integration may be prevented from occuring.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Summary] An impurity-doped layer with a fixed potential is formed on the surface of a semiconductor integrated circuit using an insulating substrate directly under the wiring channel region, thereby forming a layer between wirings. Reduce capacity and prevent crosstalk associated with higher density.

[Industrial application field]

The present invention relates to a semiconductor device using an insulating substrate such as GaAs, and particularly aims to prevent crosstalk by reducing capacitance between wirings within a device.

[Conventional technology]

In recent years, compound semiconductor devices such as HEMTs (high electron mobility transistors) using GaAs (gallium arsenide) substrates have been developed as ultrahigh-speed devices to replace current switching devices using Si (silicon) substrates. There is. These compound semiconductor devices use semi-insulating Ga as a substrate material.
Since an As substrate is used, the inter-substrate capacitance of the internal wiring has the advantage of being smaller than that of a Si element, but the coupling capacitance between wirings is larger than that of a Si element, and as the degree of integration increases, this coupling capacitance causes cross-linking between wirings. Talk can be a big problem.

FIG. 2 is a structural diagram of a conventional GaAs/HEMT (al is a cross-sectional view of the active element region forming the transistor, and (b) is a cross-sectional view of the wiring channel region through which the internal wiring of the element is passed. Among them, 2 is a GaAs substrate, 4 is an n+ type high concentration impurity doped layer formed on the surface thereof, 6 is a gate electrode such as W (tungsten) or WSi (tungsten silicide), 8 is an insulating film, and l.

are multiple wires buried within it.

The n layer 4 is formed by ion-implanting n-type impurities using the resist 12 and the gate electrode 6 as a mask, and becomes the drain D and source S regions. Although the insulating film 8 is also formed in the active element region of (al), it is omitted from the drawing because the purpose of FIG. C81 is mainly to explain the manufacturing process.

In the wiring channel region fbl, each wiring 10 has a substrate-to-substrate capacitance C+ and an inter-wiring coupling capacitance c2. As described above, the inter-substrate capacitance C1 is smaller than that of a device in which the substrate 2 is Si.

[Problem that the invention seeks to solve]

However, the coupling capacitance C2 between wirings is larger than that of a Si element. This is because although the number of lines of electric force generated from the wiring 10 is the same, in the case of a Si element, since the substrate is conductive, there are many lines of electric force between the wiring and the board, and therefore there are fewer lines of electric force between the wiring, and the number of lines of electric force between the wirings is reduced. The inter-wiring capacitance C1 is large and the inter-wiring capacitance C2 is small. On the other hand, in a GaAs element, since the substrate is insulating, the lines of electric force between the wiring and the substrate are no different from the lines of electric force that extend above the wiring (they extend evenly around the entire circumference).
Therefore, the inter-wiring capacitance C2 appears large.

In particular, as the degree of integration of devices increases, the number of required wiring channels also increases, and as the spacing between wiring becomes smaller, C2 increases.
Cucumber talk between adjacent wirings becomes a problem.

The present invention attempts to eliminate the above-mentioned drawbacks by activating the area immediately below the wiring channel region of the insulating substrate (making it a conductive layer with a fixed potential).

Means for Solving Problem c] The present invention provides a semiconductor device in which an active element region (14) is formed by adding impurities to the surface of an insulating substrate (2). There is also an impurity doped layer (20) on the substrate surface directly under the wiring channel region (16), which is different from the wiring channel region (16).
1 (20) is connected to a power source.

[Effect]

If an impurity doped layer is provided directly under the wiring channel region, this will make the insulating substrate surface conductive in the same way as the Si substrate. Therefore, although the inter-substrate capacitance C1 increases, the inter-wiring capacitance C2 decreases, so that crosstalk can be prevented. Moreover, since the overall capacity increases by only about 10%, high-speed operation is not hindered.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of the present invention, (al is a plan view, and fb is a sectional view taken along the line AA'). In the figure, 14
1 is an active element region, and 16 is a wiring channel region. The active element region 14 includes a field effect transistor (FET) Q+ with D+, G+, and Sl as drain, gate, and source electrodes, respectively, and D2 (=S+), G2 . FETQ with S2 as drain, gate, and source electrodes, respectively
2 and 2, and an inverter is formed by connecting G+S+. The drain D1 of this inverter is connected to the high potential power supply Vcc, and the drain S2 is connected to the low potential power supply Vss.
connected to. 18 indicates this grounded source electrode.

In the present invention, an impurity-doped layer 20 is formed on the surface of the substrate 2 directly under the wiring channel region 16, and its potential is fixed by a power source Vcc or VSS. In the example of FIG. 1, a portion of the layer 20 is laterally protruded and communicated with the source S2 of the active device region 14, and is fixed at ground potential. This can be done by simply changing the mask pattern used for impurity ion implantation. That is, in the past, ions were implanted using a mask that was open in the element formation region 14 and closed in the wiring channel region 16 to form a transistor as shown in FIG. N-type impurity ions may be implanted using a mask which is opened and the opening extends to the source of the active element region at the connection portion of the impurity doped layer 20 with the power source.

The above n+ type layer 20 has an inter-substrate capacitance (
Although this increases C+ in FIG. 2, the inter-wiring capacitance C2 decreases, making it possible to prevent crosstalk between adjacent wirings that accompanies higher density.

〔Effect of the invention〕

As described above, the present invention has the advantage of being able to prevent crosses between interconnects within devices of insulating base 1 anti-type semiconductor devices such as GaAs/HEMTs, which are expected to be used as ultra-high-speed devices. be.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention, and FIG. 2 is a structural diagram of a conventional GaAs/HEMT. In the figure, 2 is an insulating substrate, 4 is a source or drain region,
8 is an insulating film, 10 is a wiring, I4 is an active element region, 16 is a wiring channel region, 18 is a grounded source electrode, 2
0 is an impurity added layer.

Claims (2)

[Claims] (1) In a semiconductor device in which an active element region (14) is formed by adding impurities to the surface of an insulating substrate (2),
A wiring channel region (
16) A semiconductor device characterized in that an impurity-doped layer (20) is also formed on the surface of the substrate immediately below, and the layer (20) is connected to a power source. (2) The impurity doped layer (20) protrudes into the active element region (14) at the connection portion with the power source and communicates with the source region of the transistor formed in the active element region. The semiconductor device according to item 1.