JPS63152168A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the area of a common contact and make the size of an integrated circuit small, by connecting commonly an N-type region and a P-type region not only on a substrate surface but also in the thickness direction of the substrate in a semiconductor device having a P-N junction in the thickness direction of the substrate. CONSTITUTION:On the surface layer part of a P-type Si substrate 2, an N<+> type diffusion region 4a is formed, which is slightly larger than a contact hole 10a which is made in the next process, and on the whole surface, an insulating film 8 is stuck, which has a contact hole 10a corresponding with a region 4a. The depth of the hole 10a is set in the manner in which the hole penetrates the region 4a and reaches the middle part of the substrate 2. A metal wiring is stuck which covers the bottom surface and the side surface of the hole 10a and extends on the film 8. Thereby the region 4a and the substrate 2 are connected, and an alloy is made. Thus a small area is available for forming a common contact which makes the chip size of an integrated circuit small.

Description

Detailed Description of the Invention (Technical Field) The present invention provides a semiconductor substrate having P
Semiconductor devices with N junctions, such as power MO5FETs,
In particular, the present invention relates to a semiconductor device having a common contact connected to both a P-type impurity diffusion region and an N-type impurity diffusion region.

(Prior Art) The common contact portion will be generally described with reference to FIGS. 4 and 5.

An N-type impurity diffusion region 4 is formed on the surface of a P-type wheel crystal silicon substrate 2, and a PN junction is formed in the thickness direction of the substrate 2. In a semiconductor device having such a PN junction, when attempting to form a common contact that is connected to both the N-type impurity diffusion region 4 and the P-type head region of the substrate 2, as shown in the figure, the N-type impurity diffusion region 2 substrates within the area of 4
After forming a window 6 through which the P-type head region of is exposed on the surface and forming an insulating film 8 on the substrate 2, the contact hole 10 has a size that includes both a part of the N-type impurity diffusion region 4 and the window 6. form,
After forming the metal wiring 12, the metal wiring 12 and the substrate 2 are alloyed.

Conventional common contacts connect both the P-type head area and the N-type head area on the surface of the substrate in this way, so if the contact area does not include both the N-type area and the P-type head area, the common contact It is not possible to make ohmic contact, and therefore the area of the common contact becomes large, which is not preferable for integrated circuit devices.

(Objective) The present invention aims to reduce the area of a common contact connected to both an N-type region and a P-type head region in a semiconductor device having a PN junction in the thickness direction of a substrate, thereby reducing the size of an integrated circuit device. The purpose of the present invention is to provide a semiconductor device that can be used.

(Structure) In the present invention, the common connection between the N-type region and the P-type head region is made not only on the surface of the substrate, but also in the thickness direction of the substrate, thereby reducing the contact area.

That is, in the semiconductor device of the present invention, a first conductivity type impurity diffusion region on the front side and a second conductivity type impurity diffusion region on the inside side are formed on one main surface of the semiconductor substrate, and overlap in the thickness direction of the substrate. A contact hole is provided that penetrates a portion of the front side impurity diffusion region and reaches the inner side impurity diffusion region, and a common contact is formed that is connected to both of the impurity diffusion regions through the contact hole.

Examples will be specifically described below.

FIG. 1 is a view corresponding to FIG. 4, showing a common contact portion of the PN junction portion, and FIG. 2 is a plan view mainly showing the contact hole in that portion.

An N-type impurity diffusion region 4 a is formed on the surface of the P-type wheel crystal silicon substrate 2 . The area of the impurity diffusion region 4a is
There is no need to provide a window for the P-shaped head area of the substrate 2 within that area, and it is only necessary to have an area slightly larger than the primary contact hole.

An insulating film 8 is formed on the silicon substrate 2, and a contact hole 10a is formed in the insulating film 8. This contact hole 10a is formed to a depth that penetrates the impurity diffusion region 4a and reaches the P-type head region of the substrate 2 within the area of the impurity diffusion region 4a.

A metal wiring 12 is formed in the contact hole 10a, and in the contact hole 10a, a metal wiring 4112 is connected to both the N-type impurity diffusion region 4a and the P-type head region of the substrate 2 and alloyed.

To explain the method of forming the common contact in this embodiment, an N-type impurity diffusion region 4a is formed on the surface of the substrate 2, and the surface of the substrate 2 is covered with an insulating film 8 (see FIG. 3). Next, a resist pattern for a common contact hole is formed on the insulating film 8, and the insulating film 8 is etched by dry etching using the resist pattern as a mask. This etching is carried out until the P-type head region of the substrate 2 appears through the impurity diffusion region 4a.First, the resist is removed, the metal wiring 12 is formed, and the metal wiring 12 and the substrate 2 are heat-treated.
Alloying is carried out.

As is clear from comparing FIG. 2 with FIG. 5, the area of the contact hole 10a is smaller than the area of the contact hole 10. This is because, in this embodiment, the connection between the metal wiring 12 and the N-type impurity diffusion region 4a is made in the depth direction of the substrate 2,
This is because no area on the surface of the substrate 2 is required.

An example of a semiconductor device having a PN junction in the thickness direction of the substrate is a power MO3FET.

FIG. 6 shows the structure of a conventional power MO3FET. FIG. 6 shows the basic cell of two power MO3FETs.

An N-type epitaxial layer 22 with a low impurity concentration is formed on an N-type single crystal silicon substrate 20 with a high impurity concentration, and a P-type well 24 is formed on the surface of the epitaxial layer 22. In the P-type well 24, an N-type impurity diffusion region 26 serving as a source is formed on the surface thereof, and a window 24a is provided in the N-type impurity diffusion region 26 to expose the P-type well 24 to the substrate surface.

28 is a gate oxide film, 30 is a gate electrode, the gate electrode 30 is formed outside the N-type impurity diffusion region 26, and the well 24 between the N-type impurity diffusion region 26 and the epitaxial layer 22 is a channel region. becomes.

32 is an insulating film, and the insulating film 32 has a well window 24a.
A contact hole 34 having an area that includes both the N-type impurity diffusion region 26 and the N-type impurity diffusion region 26 is about to be formed. Reference numeral 36 denotes a metal wiring, and the metal wiring 36 is connected to both the N-type impurity diffusion region 26 and the well 24a in the contact hole 34, and is alloyed.

In this way, in conventional power MO5FETs, each basic cell is provided with one common contact with a large area, so there is a lot of wasted area, the channel area per unit area is reduced, and the on-resistance increases accordingly. There's a problem.

The on-resistance of a power MOSFET includes drain resistance, channel resistance, source resistance, and source metal ohmic resistance.The resistances mentioned above are dominant, so lowering the drain resistance and channel resistance will increase the on-resistance. It will be reduced.

Therefore, a power MO5FET to which the present invention is applied in order to lower the channel resistance is shown in FIG.

The N-type single crystal silicon substrate 20 and the N-type epitaxial layer 22 are the same as those shown in FIG. 24a is a P-type well, and an N-type impurity diffusion region 26a serving as a source is formed on the surface of the well 24. Compared to the N-type impurity diffusion region 26 of FIG. 6, this N-type impurity diffusion region 26a does not require a window for exposing the P-type head region of the well 24a to the substrate surface, so the area of the N-type impurity diffusion region 26a is 6th
It is smaller than the N-type impurity diffusion region 26 shown in the figure.

Therefore, the area of the well 24a can also be smaller than the area of the well 24 in FIG.

28 is a gate oxide film, and 30 is a gate electrode.

These are the well 24a between the N-type impurity diffusion region 26a and the epitaxial layer 22, similar to the MOSFET shown in FIG.
It is designed to cover the

32 is an insulating film, and the insulating film 32 has a contact hole 34a within the area of the N-type impurity diffusion region 26a and having a depth that penetrates the N-type impurity diffusion region 26 and reaches the P-type head region of the well 24a. It is formed.

The metal wiring 36 is connected to both the N-type impurity diffusion region 26a and the well 24a through the contact hole 34a and is alloyed.

The method for forming the common contact in this example is as follows.

This is the same method as explained in FIGS. 1 and 3.

According to the embodiment shown in FIG. 7, the area of the common contact that commonly connects the source region 26a and well 24a of the power MOSFET is reduced, and the basic cell of the power MOSFET can be made smaller. Therefore, the channel area per unit area of the conventional power MO shown in FIG.
It is wider than a 5FET and has a lower channel resistance, resulting in a smaller on-resistance.

In the embodiment shown in FIG. 7, an N-channel type power MOS is used.
Although we have explained FET, P-channel type power MO
The structure of the 5FET is exactly the same except that the conductivity type is reversed.

In the embodiments of FIGS. 1 and 7, the contact hole 10
The contact holes 10a, 34a are formed so that their side surfaces are perpendicular to the substrate surface, but the side surfaces of these contact holes 10a, 34a are formed obliquely to the substrate surface to form contact holes 10a, 34a. 34a can also be shaped like a mortar. By forming such a cone-shaped contact hole, the contact area between the impurity diffusion region on one surface side and the metal wiring can be increased.

For etching a single crystal silicon substrate in an oblique direction, wet etching using, for example, caustic soda is more convenient than dry etching.

(Effect) In the semiconductor device of the present invention, P formed in the thickness direction of the substrate
When providing a common contact in the N junction, a contact hole is formed that penetrates the first conductivity type impurity diffusion region on the front side and reaches the second conductivity type impurity diffusion region on the inside side, and the metal wiring is connected through the contact hole. Since contact is made between both impurity diffusion regions, the area required for the common contact can be reduced, and the area of the impurity diffusion region on the first surface side can also be reduced. Chip size can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a common contact portion in one embodiment, FIG. 2 is a plan view mainly showing contact holes in the same embodiment, and FIG. 3 is a schematic sectional view showing a state in the middle of manufacturing of the same embodiment. Fig. 4 is a sectional view showing a conventional common contact portion, Fig. 5 is a plan view mainly showing the contact hole in the conventional example, and Fig. 6 is a conventional power MO5FET.
7 is a cross-sectional view showing the power MO5 to which the present invention is applied.
It is a sectional view showing FET. 2...P type car crystal silicon substrate, 4a, 26a
...N-type impurity diffusion region, 10a, 34a...
...Contact hole, 12...Metal wiring, 20...N-type single crystal silicon substrate, 22...
...N type epitaxial layer, 24a...P type well.

Claims (2)

[Claims] (1) A first conductivity type impurity diffusion region on the front side and a second conductivity type impurity diffusion region on the inside side are formed on one main surface of the semiconductor substrate, overlapping in the thickness direction of the substrate, and the front side impurity diffusion region A semiconductor device comprising: a contact hole extending through a part of the inner impurity diffusion region to reach the inner impurity diffusion region; and a common contact connected to both of the impurity diffusion regions via the contact hole. (2) the surface-side impurity diffusion region is a source region;
2. The semiconductor device according to claim 1, wherein the internal impurity diffusion region is a well or a substrate and constitutes a power MOSFET.