JPH0268964A - Insulation gate type field effect transistor - Google Patents

Abstract

PURPOSE:To reduce occupation area of an element, achieve high integration easily, and increase flexibility in terms of element layout by providing a first gate electrode covering one part between a source and a drain area and a second gate electrode covering the entire area between the source and the drain area which is placed being overlapped through an insulation film on it. CONSTITUTION:An insulating gate type field effect transistor consists of a source area 3 and a drain area 4 formed on a semiconductor substrate and a plurality of gate electrodes 1 and 2 which exists between those source and drain areas 3 and 4 and is extended in insulated status, a first gate electrode 1 is placed on only one part between the source and the drain areas a and 4 being overlapped, the second gate electrode 2 overlaps to the above first gate electrode 1 through an insulation film 8, and it is placed so that it covers the entire area between the source and the drain areas 3 and 4. For example, the gate length of the gate electrode 1 is set to 2mum, the gate width is set to 2mum, the gate length of the gate electrode 2 is set to 1.2mum, and the gate width is set to 20mum. Also, areas 10 and 11 for each contact between the gate electrode 1 and the gate electrode 2 is placed at the same side.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to insulated gate field effect transistors.

2. Description of the Related Art In recent years, semiconductor integrated circuits are of the MOS type (M
etal −0xide −Sen+1 conduct
(or) field effect transistors are leading the way, and in order to improve the degree of integration, element size rules have been made finer and circuit layouts have been devised.

Among these, a conventional example of a circuit layout related to the present invention is shown in FIG. The figure is one source.

A transistor circuit has two gate electrodes for the drain region, and there are two gate electrodes between gate electrode 1 and gate electrode 2.
A region is provided to insulate the gate electrode and source and drain regions of the seed. This is a thick insulating film made of silicon dioxide used to isolate each element in a typical integrated circuit. By overlapping gate electrodes 1 and 2 on this thick insulating film, the source and drain are isolated.

When the gate length and gate width are specified as shown in the figure,
If the gate widths of gate electrodes 1 and 2 are significantly different, the gate width will be different when voltage is applied to gate electrode 1 and when voltage is applied to gate electrode 2 for the same drain applied voltage. A drain electrode proportional to the ratio can be obtained. The transistor can have two types of drain current capability for exactly one source and drain region.

Problems to be Solved by the Invention In the general circuit layout described above, a region for separating the gate electrodes, that is, a region for forming the thick insulation III 9, is required between the gate electrodes 1 and 2. Pad regions 10 and 11 are required to make contact with the metal wiring formed in the upper layer of transistors and transistors 2, and as shown in FIG. shall be.

Means for Solving the Problems As shown in FIG. 1, the semiconductor device of the present invention includes a first gate electrode disposed to cover only a portion between the source and drain regions, the source, A second gate electrode is provided which covers the entire area between the drain regions and is arranged to overlap the first gate electrode with an insulating film 8 interposed therebetween.

Effects According to the above structure, there is no need for a separation region between the two gate electrodes, and each region for contact with the upper layer wiring can also be formed on the same side, so higher integration is possible. , the degree of freedom in layout increases.

Embodiment The present invention will be explained based on the plan view and sectional view of the embodiment device shown in FIGS. 1(a) and 1(b). In the figure, a semiconductor substrate (
For example, on a silicon substrate, a source region 3, a drain region 4, and an insulating film region 5 for element isolation are arranged around them. As shown in FIG. 6(b), a gate insulating film (silicon dioxide film) 6 of 250 Å is grown on the semiconductor substrate, and then a gate electrode 1 is formed of polycrystalline silicon with a thickness of 3,000 Å.
Form with thickness A. The gate electrode 1 does not completely separate the source and drain regions, but only partially covers them. Similarly, a gate electrode 2 is formed with polycrystalline silicon to a thickness of 3000 nm on the gate insulating film 250A,
The source and drain regions are separated by the gate electrode 1 and the gate electrode 2, and the gate electrode 2 is placed over the gate electrode 1 with a silicon dioxide film 8 of 2000 Å interposed therebetween. The gate length of gate electrode 1 is 2 μm and the gate width is 2 μm.
, and the gate length of the gate electrode 2 is 1.2 μm, and the gate length is 20 μm. Further, the contact regions 10 and 11 for the gate electrode 1 and the gate voltage 2 are arranged on the same side.

Now, if the transistor formed in this way is an enhancement type transistor, if a voltage is applied to gate electrode 1 while the drain electrode is applied, but no voltage is applied to gate electrode 2, the channel part under gate electrode 1 In the opposite case, current flows only in the lower channel portion of the gate electrode 2. If the gate electrode 1 is a transistor I and the gate electrode 2 is a transistor (2), two types of current values can be obtained in which the amount of drain current differs by more than 10 times between transistors (E) and (2). The ratio of the drain current values of the transistors E and ■ can be set by changing the ratio of the gate widths of the respective gate electrodes, but it is also possible to set the ratio by changing the gate length, or by adding boron, etc. to the surface of the semiconductor substrate under each gate electrode. By ion-implanting impurities, the characteristics of each transistor can be changed.

Effects of the Invention As explained above, the present invention has a structure in which two gate electrodes are stacked on one source and drain in the gate width direction, so the area occupied by the device is small (high integration is easy). This increases the degree of freedom in element layout.

[Brief explanation of the drawing]

1(a) and 1(b) are a plan view and a sectional view of a field effect transistor showing an embodiment of the present invention, and FIG. 2 is a plan view of a conventional example. l... Gate electrode, 2... Gate electrode, 3... Source region, 4... Drain region, 5... Separation region ( thick insulation film), 6...
...Gate insulating film of gate electrode 1, 7...
Gate insulating film of gate electrode 2, 8.9...Insulating film, 10.11...Contact region layer Figure 1-11 Gate electrode immersion 2---Gate electrode 8-m - Distance training 1 trap 10.11-11 ke °'-) At the upper layer fζ 8 list □ Kokotact 4Xj da (. Figure

Claims (1)

[Claims] Consisting of a source region and a drain region formed on a semiconductor substrate, and a plurality of gate electrodes extending in an insulating state between these source and drain regions, the first gate electrode is located in a portion between the source and drain regions. The second gate electrode is arranged to overlap only the first gate electrode with an insulating film interposed therebetween, and is arranged to cover the entire area between the source and drain regions. An insulated gate field effect transistor.