JPH03291959A - Semiconductor device - Google Patents

Abstract

PURPOSE:To realize that a semiconductor device becomes fine and is integrated highly by a method wherein a difference in level is formed on the surface of a semiconductor device and an element isolation region is formed in the difference in level in order to reduce the width and the area of an element isolation layer and to form the element isolation region in a self-aligned manner. CONSTITUTION:An element isolation layer 3 formed in a difference in level on the surface of a semiconductor substrate 1 is provided. For example, a difference in level is formed in the thickness direction inside a semiconductor substrate 1; the difference is level is used as an element isolation layer 3; impurity diffusion layers 4 are formed so as to sandwich the element isolation layer 3. An inversion-preventing layer 2 is formed on the lower-part sidewall of the element isolation layer 3. The element isolation layer 3 is used to insulate the impurity diffusion layers 4 physically and electrically; generally, it is formed of an insulating film such as an oxide film, a nitride film or the like; its thickness is decided by a dielectric breakdown strength. The inversion-preventing layer 2 is a layer which prevents the semiconductor substrate 1 from becoming a belt of an opposite conductivity type along the element isolation layer 3; generally, it is a layer whose conductivity type is the same as that of the semiconductor substrate 1 and whose concentration is larger than that of the substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device having element isolation that physically and electrically isolates semiconductor elements such as transistors and resistors.

[Summary of the Invention] A semiconductor device having a plurality of semiconductor elements, in which a step is formed on the surface of a semiconductor substrate, and an element isolation layer is formed in a region including the step.

[Prior Art] A conventional element isolation layer is formed two-dimensionally in a flat region. That is, as shown in FIG. 6, the element isolation layer 63 and the impurity diffusion layer 64 were formed planarly on the semiconductor surface, and had a fixed distance and area as an element isolation region.

[Problem to be Solved by the Invention 1] Since the device isolation region has a certain distance and area, it has been an obstacle to miniaturization and high integration of semiconductor devices.

[Means for Solving the Problem] A step is formed on the surface of a semiconductor substrate, and an element isolation region is formed in the step.

[Operation] Since the step is used as an element isolation region, the element isolation region can be made smaller in plan view (on the mask). Furthermore, it becomes possible to form the element isolation region in a self-aligned manner, and the element isolation region can be made as small as the thickness of the element isolation layer.

【Example] A cross-sectional view of a semiconductor device showing a first embodiment is shown in FIG.

As shown in FIG. 1, a step is formed in the thickness direction within the semiconductor substrate 1, and the step becomes the element isolation layer 3. An impurity diffusion layer 4 is present across the element isolation layer 3. Further, an anti-inversion layer 2 is present on the lower sidewall of the element isolation layer 3. The element isolation layer 3 physically and electrically insulates the impurity diffusion layers 4 from each other. The element isolation layer 3 is generally an insulating film such as an oxide film or a nitride film. When the element isolation layer 3 is an insulating film, its thickness is determined by the dielectric strength voltage.1 The inversion prevention layer 2 is a layer that prevents the semiconductor substrate 1 from becoming a reverse conductive band along the element isolation layer. Generally, it is a layer having the same conductivity type as the semiconductor substrate 1 and having a higher concentration than the substrate.

Of course, this anti-inversion layer 2 is unnecessary if there is no risk of inversion. Although FIG. 1 shows only the impurity diffusion layer 4 as an element, it goes without saying that elements such as transistors, low-voltage antibodies, and capacitors are also included. 6 Now, FIG. 1 shows vertical steps, The depth of this step becomes the length of element isolation. However, as can be easily seen, the length of element isolation in plan view is only about the thickness of the element isolation layer 3. If the single selective oxidation method is used, a length of element isolation of 1 μm or more is required. The planar length of the element separation of the invention is 1
um or less is also possible. There is no need to consider the length of element isolation on the mask, and the impurity diffusion layer 4 is also formed in a self-aligned manner.

Although Figure 1 considers vertical steps, the situation is the same for slope-type steps. FIG. 2 shows a cross-sectional view of a semiconductor device according to a second embodiment. That is, as shown in FIG. 2, an element isolation layer 13 is formed in a sloped step portion. In the case of the slope-type step shown in FIG. 2, the actual length of element separation corresponds to the length of the slope step, and is shorter in plan. When the length of the step on the slope is 4 and the angle of inclination of the slope with respect to the horizontal plane is θ, the length of planar element separation is βCOSθ. Therefore, although the length (width) of element isolation is longer than in the case of the vertical step shown in Figure 1, it is not only shorter than the actual element isolation length, but also there is no need to consider the element isolation length on the mask. The length of element isolation is determined in a self-aligned manner. That is, the length of element isolation is determined by the length of the slope or the difference in level.

Now, the feature of the element isolation layer of the present invention is that the length of the element isolation layer (
Not only can the length (width) be made smaller, but there is no need to consider the length (width) of the element isolation layer on the mask because the length is determined in a self-aligned manner.1. (width) is, in FIG. 2, where β is the length of the slope, θ is the inclination of the slope with respect to the plane, and t is the thickness of the element isolation layer.
In a plane (viewed from above), habo rt2 cos θ ten t
/sin θ'' From this equation, when θ=90°, the length (width) of the element isolation layer is the smallest and equal to the thickness t of the element isolation layer.

In FIGS. 1 and 2, the case where the element isolation layer is formed on the step on the surface of the semiconductor substrate is explained, but the element isolation layer may also be formed in the region around the step including the step. The device isolation layers 33 in FIG. 3 and 43 in FIG. 4 are shown in cross-sectional views of the semiconductor device showing the third embodiment. ing. In these cases, it goes without saying that a special mask for element isolation is required, but compared to the case where an element isolation layer is formed only on flat areas, ), the device isolation layer can be made smaller. It goes without saying that it can also be used in combination with a conventional element isolation layer formed only on flat areas.

FIG. 4 shows a sectional view of a semiconductor device showing a fourth embodiment.

Figure 3 illustrates the case where vertical steps are included.
It goes without saying that what is described in FIG. 3 can also be applied to the slope type step shown in FIG. 4.

As yet another embodiment, the present invention can be applied to an element isolation method that electrically isolates elements. FIG. 5 shows a sectional view of a semiconductor device showing a fifth embodiment. That is, as shown in FIG. 5, a step is formed at a location that will become an element isolation region, and an insulating film 53 and an electrode 55 for element isolation are formed on the step. These insulating film 53 and electrode 55 for element isolation correspond to the element isolation layer described in FIGS. 1 to 4.

By adjusting the voltage applied to the 1i pole 55 for element isolation, the impurity diffusion layers 54 (element regions) can be isolated from each other. Moreover, it goes without saying that the same thing as shown in FIG. 5 can be said in the case of a slope type step.

Although FIGS. 1 to 5 show a simple structure centered on the element isolation region, a wiring layer, an insulating film between the eyebrows, and a protective film layer are formed in addition to the structure shown in the above figures.

Needless to say, the product is completed.5 [Effect of the invention 1] As explained above, in the semiconductor device of the present invention, the element isolation region is formed in the step formed on the surface of the semiconductor substrate. Width and area can be reduced. Particularly in plan view, the width of the element isolation layer can be made as small as the thickness of the element isolation layer. Furthermore, element isolation regions can be formed in the stepped portions in a self-aligned manner.

Therefore, it has the greatest effect on miniaturization and high integration of semiconductor devices.

[Brief explanation of drawings]

1 is a sectional view of a semiconductor device showing a first embodiment, FIG. 2 is a sectional view of a semiconductor device showing a second embodiment, and FIG. 3 is a sectional view of a semiconductor device showing a third embodiment.
4 is a sectional view of a semiconductor device showing a fourth embodiment, FIG. 5 is a sectional view of a semiconductor device showing a fifth embodiment, and FIG. 6 is a conventional semiconductor device. FIG. 1, 11. 2, l 2. 3, 13. 4, 14. 53 ・ ・ ・ 55 ・ ・ ・ β ・ ・ ・ θ ・ ・ 31, 4 32, 4 33, 4 34, 4 1, 51, 61 ・Semiconductor substrate 2.52.62 ・Inversion prevention layer 3.63 ・Element Min&ii (insulating) layer 4.54.64 ・Impurity diffusion layer ・Insulating film ・Element isolation electrode ・Length of the step on the slope ・Inclination angle t between the slope and the flat part・・・・・・・Element At least the thickness of the separation layer

Claims (1)

[Claims] A semiconductor device having an element isolation layer formed on a step on the surface of a semiconductor substrate.