198766 A 6 B 6 經濟部中央標準局員工消費合作社印裝 五、發明説明（） 1 發明的背景 1.發明的領城 本發明為關於半導髏裝置，具有一隔離^在物理上及 電氣上隔離半導體元件，類如電晶體：電阻及其類似者。 2 .有關枝術之説明 該隔離層以前乃在平坦區域平坦地構成。如圖6所示 ，例如，一隔離層的及一雜質擴散層64皆在該半導體基 體表面的同一平面構成，該隔離區有一預先設定的距離與 地區。 半導體裝置之微小型化與高密度統合甚為困難，因為 該隔離區需要預先¥定的距離與地區。 # 太發明概略 為了達到半導體装置之微小型化與高密度統合，乃在 該半導體基體的表面溝成階級（或槽溝），及在該等階级 (或該等槽溝的邊牆）上構成隔離區。雜質擴散層則配置 於半導體基體的平面表面上，此處成為作用區。由於階级 或該槽溝的邊牆作為隔離區之用，於是可以減少在平面上 所見的隔離區。更可以在自動對準方式構成該隔離區，以 及因而減低該隔離區至於該隔離層的厚度。 圖簡略説明 圖1為按照第一寶例之半導體裝置的剖視圖； (請先閲讀背面之注意事項再塡寫本頁) 中 4(2丨，）X297公蝥）80. 5. 20,000»(H) 198766 A 6 B 6 經濟部中央標準局員工消费合作社印^ 五、發明説明（2 ) 圖2為按照第二實例之半導髏裝置的剖視圖； 圖3為按照第三實例之半導髏裝置的剖視圔； 圖4為按照第四實例之半導體裝置的剖視圖； 圖5為按照第五實例之半導體裝置的剖視圖；及 圖6為表示一傳統的半導體裝置之剖視圖； 圖7 a —圖7 h為為構成圖1之本隔離結構的階级之 詳細順序。 本發明^詳紬説明 圖1為一按照第一實例之半導體裝置的剖視圖。如圖 1所示，在半導體基體1内，照箸厚度的方向構成階级（ 檣溝的邊牆），以便ί乍為隔離層3之用。雜質擴散層4則 被夾在該等隔離層3之間。此外，在該隔離層3的下面部 分（在該隔離層的背面表面上）上的邊牆上有逆轉保護層 2存在著。該隔離層3使該等雜質擴散層4物理上及電氣 上相互絶緣。該等隔離靥3通常是以類似氣化物薄膜或氮 化物薄膜之絶緣薄膜所組成。當該等隔離層3由絶緣膜組 成，其厚度則視絶緣膜之破壞電壓而定。該逆轉保護層2 的功用為防止該半導體基體1沿著該等隔離靥成為一逆向 傳導區，以及通常具有與半導體基體1同樣形態之導電性 ，和更較該基體為大的集中。倘若無逆化的可能性時，則 逆轉層2並不需要。雖則圖1只將該雜質擴散層4以元件 表示，但無需指出者，該等類如電晶體、電阻器及電容器 ，當然是可包括在該等元件之中。這褢，圖1表示垂直贈 ................................·,...........裝·：··.......................ΤΤ............................線- (請先閱讀背面之注意事項再填寫本頁) V 4(21(1Χ297公釐）80. 5. 20,000張（Η) 198766 A 6 B 6 經濟部中央標準局貝工消費合作社印製 五、發明説明（3 ) 级及其深度決定該隔離的長度。不過，很容易了解，該隔 離長度，為在平面上所見，只是差不多與該等隔離層3的 厚度相等。雖然局部氧化作用需要隔離具有較1 為大 的長度。在構成一個罩子，可無需考盧與隔離長度相當的 部分。該雜質擴散層4亦可以自動對準構成。 圖1表示該垂直階级。然而，即使是傾斜面的階级， 亦可適用。圖2為按照第二實例之半導體裝置的剖視圖。 即，為圖2所示，隔離層13在該等傾斜面的階级構成。 在為圖2所示之傾斜面的該等階级的情形褢，該實質的隔 離長度相當於該傾斜面之階級的長度，且自上面看來較短 。若是以2表示該傾斜面之階级的長度，及與水平面相閬 之傾斜面的傾斜角度為0,則自平面所見之隔離的長度為 2c o s Θ。因此，雖然自圖2之平面看來的隔離長度（ 寬度）要比圖1中所示的情形之垂直階级為長，其長度卻 仍比實質的隔離為短。當該罩經已構成，再無需考慮到相 當於該隔離長度的部分，卽，該隔離長度是以自動對準方 式確定。即，該隔離良度是由該傾斜面或由該階级的長度 決定。 按照本發明的隔離層，其特徴在於當構成該罩子時， 無需考慮該隔離靥的長度（寬度），由於它不但容許減少 在平面上之隔離層的長度（寬度），且以自動對準方式決 定其長度。在圖2褢，若將該傾斜面的長度以2表示，該 傾斜面之傾斜度與平面關係以0表示，及該隔離層的厚度 以t表示，則按照本發明，隔離層的長度（寬度）在平面 (請先閱讀背面之注意事項再塡寫本頁) 甲 4 (210X297公釐）80. 5. 20,000張（H) 3BS5S$ 198766 A6 一 _B 6 _ 五、發明説明（4 ) (請先閲讀背面之注意事項再蜞寫本頁) 上（由上面方向看）差不多成為2cose + tsinS 。由此方程式，該隔離層的長度（寬度）當0 = 90°時 為最小，並成為等於該隔離層的厚度t。 圖1及圖2已解說過該裝置，其中該等隔離層為在該 半導體基體之表面的階级上構成。不過，亦得以在該等階 级周圍，包括該等階级在内，構成隔離層。圖3為按照第 三實例之半導體裝置的剖視圖。即，依據圖3及圖4,該 等隔離層33及43皆不但於該等階级上構成，且亦在平 坦部分（平面部分）之上。在這些情形褢，可無需指出， 需要有一作為隔離之用的特別罩子。不過，其隔離的寬度 與當該隔離層只在平坦部分構成的的情形相比，可在平面 上（自上面方向看）減少。自然，這是得以將之與只在平 坦部分構成之傳統的隔離層合併使用。 圖4為按照第四實例之半導體裝置的剖視圖。 圖5為表示包括垂直階级的情形。不過，無需提醒者 ,參照圖3所說明的事項，亦適合於如圖4所示之傾斜面 的階级上。 經濟部中央標率局w工消費合作社印躲 按照另一實例，本發明可適合於一項以電氣上隔離該 等元件的隔離方法。圖5為一按照第五實例之半導體裝置 的剖視圔。如圖5所示，此乃構成於隔離區之一階级，和 一絶緣膜53及一電極55，皆在該階级上構成，以為隔 離之用。該作為隔離之用的絶緣膜53與電極55相當於 圖1至圖4所說的之用關的隔離層。將作為隔離之用的電 極5 5的電壓予以調整，則可將雜質擴散層54 (元件區 (210X297公釐）80. 5. 20,000¾ (H) , 198766 A6 B 6 五、發明説明（5 ) (請先閱讀背面之注意事項再填寫本頁) 域）相互隔離。此外，關於圔5所說明之同一物件，亦能 適合於該等傾斜面之該等階级的情形。 自圖1至圖5，己解説了首先討論該隔離區之簡單結 構，不必指出者，除上面圖不的結構不的結構外，該産品 乃由佈線層，内層絶綠膜與保護層構成而完成。 經濟部中央標準局員工消费合作社印裝 圖7 a —圖7 h表示一構成圖1之本隔離結構之各階 段的詳細的順序。在該第一階段，照相抗蝕劑2模製在半 導體基體1上。一半導體基體以單一元件類如矽或鍺製成 ，或一半導體化合物類如砷化鎵（GaAs)、磷化絪（ InP),皆作為如同該半導體基體1 (圖7a)之用。 在第二階段，在半導體基體1内之無照相抗蝕劑2的區域 ，以乾蝕刻方法或濕蝕刻方法予以蝕刻並構成一槽溝。該 在半導體基髏1内之蝕刻部分的深度，在本發明褢為一隔 離寬度。因此，該蝕剝量（蝕剝深度），則視所需隔離的 寬度而定（圖7. b) 3在第三階段裏，於移去相照抗蝕劑 之後，構成一絶緣膜4以及聚積在該薄絶緣膜4上面的氮 化矽膜5。該絶緣膜乃以氧化矽或氮氣化矽製成。該絶緣 膜4的厚度以100-1000 A為佳。該氮化矽膜5 的作用，為如同抗阻氧化的罩子。其他的材料之可抗阻氣 化者，可取代氮化矽作為抗阻氧化的罩子。該氮化矽5的 厚度，通常約為200 — 1 0 0〇〇 A ,以便不致有針孔並 且足夠抗阻氧化的特質。化學蒸氣沉澱法（CVD方法） 或物理蒸氣沉澱法（PVD方法）則用作構成氮化矽膜5 之用（圖7c)。在第四階段褢，該氮化矽膜5聚積在階 中 4 (21ΠΧ297公釐）80. 5. 20,000張（H〉 198766 A6 一 B 6 經濟部中夬標準局員工消費合作社印製 五、發明説明（6 ) •級部分則被移去。該聚積於階级部分之氮化矽膜5較聚積 在平面表面部分者被較快地移去，由於以CVD方法或P VD方法聚積在階级部分之氮化矽膜5,較在平面表面部 分易於蝕刻。無氮化矽膜5之等方性蝕刻以構成區域6較 異方性蝕刻為有效。即，濕蝕刻或等方性乾蝕刻較有效地 將在階级部分之氮化矽膜蝕去，而在平面表面部分的氮化 矽’留著，尤其當氮化矽膜5以游離氣CVD方法或噴鍍方 法之一製成者，因為以此項方法製成的氮化矽膜乃極易碎 製者（圖7 d)。在第五階段，以將雜質導入該區域6 ( 邊牆），構成一逆轉保護層而無氮化矽膜保護該逆轉場。 該等雜質皆用離子植入法或擴散法（圔7 e)導入。在第 六階段褢，作為隔離用的絶緣膜8在區域6構成，而無因 氣化該半導體基體1之氮化矽膜。當該基體1為以矽製的 時，該絶綠膜8為一氧化矽膜。在第七階段，該氮化矽膜 5 _與該薄絶緣膜4則波移去。該等區域未以作為隔離之用 的絶緣膜8遮蓋者，皆為作用區。例如，雜質擴散層1〇 乃以經由一預先構成於半導體基體之表面部分的薄絶緣膜 9以離子植入構成。於是，形成電晶體，金靥線及鈍化層 而完成一半導體裝置。此上述之過程，為如圖1之製造該 結構的一値實例。無需言宣者，尚有種種其他製造此結構 的方法。在圖2—圖5衷所示結構，亦皆為以上述相類的 方法之一製造者。 如上述之本發明的半導體裝置褢，該隔離區皆在該等 構成在半導體基體的表面上之該等階鈒上構成，以減小該 (請先閲讀背面之注意事項再填寫本頁) 甲 4(21ΠΧ297公釐）80· 5. 20,000張（H) ^5^198766 A 6 B 6 五、發明説明（7 ) 等隔離層的寬度與面凟。尤其由上面看該隔離層的寬度， 可減少該隔離層的厚度。再者，該等隔離層在階级上是自 動對準方式構成。因此，該半導體裝置可精美地以高度積 體形式製造。 < .............................................i'............................ΤΓ......................埠 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局S工消費合作社印製 甲4(21(以297公蝥）80.5.20,000張（1^) 0198766 A 6 B 6 Printed by the Employees ’Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of the invention (1) The background of the invention 1. The invention of the invention The invention relates to a semi-conductor device, with an isolation ^ physical and electrical Isolate semiconductor components, such as transistors: resistors and the like. 2. Remarks on branch technique The isolation layer was previously formed flat in a flat area. As shown in FIG. 6, for example, an isolation layer and an impurity diffusion layer 64 are both formed on the same plane of the surface of the semiconductor substrate, and the isolation region has a predetermined distance and area. The miniaturization and high-density integration of semiconductor devices are very difficult because the isolation area requires a predetermined distance and area. # Tai invention outline In order to achieve the miniaturization and high density integration of semiconductor devices, grooves (or grooves) are formed on the surface of the semiconductor substrate, and on these levels (or side walls of the grooves) Constitute a quarantine area. The impurity diffusion layer is arranged on the planar surface of the semiconductor substrate, where it becomes the active region. Since the class or the side wall of the trench is used as an isolation zone, the isolation zone seen on the plane can be reduced. It is also possible to form the isolation region in an automatic alignment mode, and thus reduce the thickness of the isolation region as far as the isolation layer. Brief description of the drawings Figure 1 is a cross-sectional view of a semiconductor device according to the first example; (please read the precautions on the back before writing this page) 4 (2 丨,) X297 public slug) 80. 5. 20,000 »(H ) 198766 A 6 B 6 Printed by the Employees ’Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs ^ V. Description of the invention (2) FIG. 2 is a cross-sectional view of the semi-conductor device according to the second example; FIG. 3 is a semi-conductor device according to the third example 4 is a cross-sectional view of a semiconductor device according to a fourth example; FIG. 5 is a cross-sectional view of a semiconductor device according to a fifth example; and FIG. 6 is a cross-sectional view showing a conventional semiconductor device; FIGS. 7 a-7 h is the detailed order of the classes constituting the isolation structure of FIG. 1. DETAILED DESCRIPTION OF THE INVENTION FIG. 1 is a cross-sectional view of a semiconductor device according to a first example. As shown in FIG. 1, in the semiconductor substrate 1, a tier (a side wall of a groove) is formed according to the thickness direction of the chopsticks, so that it is used as the isolation layer 3. The impurity diffusion layer 4 is sandwiched between the isolation layers 3. In addition, a reverse protection layer 2 is present on the side wall on the lower part of the isolation layer 3 (on the back surface of the isolation layer). The isolation layer 3 physically and electrically insulates the impurity diffusion layers 4 from each other. The isolator 3 is usually composed of an insulating film similar to a vapor film or a nitride film. When the isolation layers 3 are composed of an insulating film, the thickness depends on the breakdown voltage of the insulating film. The function of the reversal protective layer 2 is to prevent the semiconductor substrate 1 from becoming a reverse conduction region along the isolation elements, and generally has the same form of conductivity as the semiconductor substrate 1, and is more concentrated than the substrate. If there is no possibility of reversal, then reversal layer 2 is not required. Although FIG. 1 only shows the impurity diffusion layer 4 as an element, it need not be pointed out that such types as transistors, resistors, and capacitors can of course be included in these elements. In this case, Figure 1 shows a vertical gift ............................................ ... install ...: ........................ ΤΤ .................. .......... Line-(Please read the precautions on the back before filling out this page) V 4 (21 (1Χ297 mm) 80. 5. 20,000 sheets (Η) 198766 A 6 B 6 Ministry of Economic Affairs Printed by the Beigong Consumer Cooperative of the Central Standards Bureau. The description of invention (3) and its depth determine the length of the isolation. However, it is easy to understand that the length of the isolation, as seen on the plane, is almost the same as that of the isolation layer The thickness is equal. Although local oxidation requires isolation to have a greater length than 1. In forming a cover, it is not necessary to take a part of Kaulu equivalent to the isolation length. The impurity diffusion layer 4 can also be automatically aligned. Figure 1 shows this Vertical class. However, even the inclined plane class can be applied. FIG. 2 is a cross-sectional view of the semiconductor device according to the second example. That is, as shown in FIG. 2, the isolation layer 13 is on the inclined plane class In the case of these classes for the inclined plane shown in Figure 2, the substantial separation length is equivalent to the inclination The length of the plane of the face, and it seems shorter from above. If the length of the class of the inclined plane is represented by 2, and the inclination angle of the inclined plane relative to the horizontal plane is 0, the length of the isolation seen from the plane is 2c os Θ. Therefore, although the isolation length (width) from the plane of Figure 2 is longer than the vertical level of the situation shown in Figure 1, its length is still shorter than the actual isolation. When the cover After being constructed, it is no longer necessary to consider the part corresponding to the isolation length. That is, the isolation length is determined by automatic alignment. That is, the isolation goodness is determined by the inclined plane or the length of the class. The special feature of the isolation layer of the present invention is that when the cover is formed, it is not necessary to consider the length (width) of the isolation lug, because it not only allows the length (width) of the isolation layer on the plane to be reduced, but also is determined by the automatic alignment According to the present invention, according to the present invention, if the length of the inclined surface is represented by 2, and the relationship between the inclination of the inclined surface and the plane is represented by 0, and the thickness of the isolation layer is represented by t, length( Width) on a flat surface (please read the precautions on the back before writing this page) A 4 (210X297 mm) 80. 5. 20,000 sheets (H) 3BS5S $ 198766 A6 I_B 6 _ V. Description of the invention (4) (Please read the precautions on the back before writing this page) On (looked from above) it becomes almost 2cose + tsinS. From this equation, the length (width) of the isolation layer is the smallest when 0 = 90 ° and becomes It is equal to the thickness t of the isolation layer. The device has been illustrated in FIGS. 1 and 2 in which the isolation layers are formed on the surface of the semiconductor substrate. However, it is also possible to form an isolation layer around these levels, including these levels. Fig. 3 is a cross-sectional view of a semiconductor device according to a third example. That is, according to FIG. 3 and FIG. 4, the isolation layers 33 and 43 are not only formed on the classes, but also on the flat part (planar part). In these cases, it is not necessary to point out that a special cover for isolation is needed. However, the width of the isolation can be reduced in the plane (as viewed from above) compared with the case where the isolation layer is formed only on a flat portion. Naturally, this allows it to be combined with the traditional isolation layer that is composed only of flat parts. 4 is a cross-sectional view of a semiconductor device according to a fourth example. Fig. 5 shows a situation including vertical classes. However, it is not necessary to remind people that the matters explained with reference to FIG. 3 are also suitable for the class of inclined surfaces as shown in FIG. According to another example, the present invention can be adapted to an isolation method for electrically isolating these components. Fig. 5 is a sectional view of a semiconductor device according to a fifth example. As shown in FIG. 5, this is a class formed in the isolation region, and an insulating film 53 and an electrode 55 are formed on the class for isolation. The insulating film 53 and the electrode 55 for isolation correspond to the isolation layer described in Figs. 1 to 4. By adjusting the voltage of the electrode 5 5 for isolation, the impurity diffusion layer 54 (element area (210X297 mm) 80. 5. 20,000¾ (H), 198766 A6 B 6 V. Description of the invention (5) (Please read the precautions on the back before filling this page) Field) Separated from each other. In addition, the same object described in 圔 5 can also be adapted to the situation of the classes of the inclined surfaces. From Figure 1 to Figure 5, the simple structure of the isolation area is first discussed. It is not necessary to point out that, except for the structure not shown in the above figure, the product is composed of a wiring layer, an inner green film and a protective layer. carry out. Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. Figures 7a–7h show the detailed sequence of the stages that make up the isolation structure of Figure 1. In this first stage, the photoresist 2 is molded on the semiconductor substrate 1. A semiconductor substrate is made of a single device such as silicon or germanium, or a semiconductor compound such as gallium arsenide (GaAs) or phosphide (InP) is used as the semiconductor substrate 1 (Figure 7a). In the second stage, the areas in the semiconductor substrate 1 where there is no photoresist 2 are etched by dry etching or wet etching and a trench is formed. The depth of the etched portion in the semiconductor base 1 is a separation width in the present invention. Therefore, the amount of erosion (depth of erosion) depends on the width of the required isolation (Figure 7. b) 3 In the third stage, after removing the photoresist, an insulating film 4 and The silicon nitride film 5 accumulated on the thin insulating film 4. The insulating film is made of silicon oxide or silicon nitride. The thickness of the insulating film 4 is preferably 100-1000 A. The silicon nitride film 5 functions as a hood that resists oxidation. Other materials that can resist gasification can replace silicon nitride as a cover to resist oxidation. The thickness of the silicon nitride 5 is usually about 200-1000 A, so as not to have pinholes and is sufficiently resistant to oxidation. The chemical vapor deposition method (CVD method) or the physical vapor deposition method (PVD method) is used to form the silicon nitride film 5 (FIG. 7c). In the fourth stage, the silicon nitride film 5 was accumulated in the stage 4 (21ΠΧ297 mm) 80. 5. 20,000 sheets (H> 198766 A6-B 6 Printed by the Employee Consumer Cooperative of the China Bureau of Standards, Ministry of Economic Affairs V. Inventions Explanation (6) • The level part is removed. The silicon nitride film 5 accumulated in the class part is removed more quickly than those accumulated on the planar surface part, because it is accumulated in the class by the CVD method or the P VD method Part of the silicon nitride film 5 is easier to etch than on the planar surface portion. The isotropic etching without the silicon nitride film 5 is more effective than the anisotropic etching to constitute the region 6. That is, wet etching or isotropic dry etching is more effective The silicon nitride film in the gradation part is etched away, and the silicon nitride 'in the planar surface part remains, especially when the silicon nitride film 5 is made by one of the free gas CVD method or the sputtering method, The silicon nitride film produced by this method is extremely fragile (Figure 7d). In the fifth stage, impurities are introduced into the area 6 (side wall) to form a reverse protective layer without silicon nitride film Protect the reversal field. These impurities are introduced by ion implantation or diffusion method (圔 7 e). In the sixth order The insulating film 8 for isolation is formed in the region 6 without vaporizing the silicon nitride film of the semiconductor substrate 1. When the substrate 1 is made of silicon, the green film 8 is a silicon monoxide film In the seventh stage, the silicon nitride film 5_ and the thin insulating film 4 are removed. Those areas not covered by the insulating film 8 for isolation are the active areas. For example, the impurity diffusion layer 10 is formed by ion implantation through a thin insulating film 9 pre-constructed on the surface portion of the semiconductor substrate. Thus, a transistor, a gold line and a passivation layer are formed to complete a semiconductor device. The above process is as follows Figure 1 is an example of manufacturing this structure. There is no need to declare, there are various other methods of manufacturing this structure. The structures shown in Figures 2 to 5 are also manufactured by one of the above-mentioned similar methods. As described above for the semiconductor device of the present invention, the isolation regions are all formed on the steps formed on the surface of the semiconductor substrate to reduce this (please read the precautions on the back before filling this page) A 4 (21ΠΧ297 mm) 80 · 5. 20,000 sheets (H) ^ 5 ^ 198766 A 6 B 6 V. Description of the invention (7) The width and surface area of the isolation layer. Especially the width of the isolation layer can be seen from above, which can reduce the thickness of the isolation layer. Furthermore, the isolation layers are in class The upper part is composed of automatic alignment. Therefore, the semiconductor device can be beautifully manufactured in a highly integrated form. ≪ ......................... .................... i '............................ ΤΓ ...................... port (please read the precautions on the back before filling in this page) Printed A 4 by the S Industry and Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy (21 (to 297 male candidates) 80.5.20,000 sheets (1 ^) 0