JPH01236648A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To contrive the microscopical formation of an element and an increase in the integration of the element by a method wherein the element is formed into a structure, wherein insulating films on the side surfaces of word lines and trenches for a capacitor are brought into contact with each other at least a part of each of their surfaces or side surfaces. CONSTITUTION:An oxide film 12 for interelement isolation is formed in a trench for isolation and a capacitor plate 17 is formed in trenches for a capacitor between the film 12 and insulating films 15 on the side surfaces of word lines 14. That is, an element is formed into a structure, wherein a trench capacitor and a trench isolation are provided and the gate insulating films 15 on the side surfaces of the word lines 14 and the trenches for a capacitor come into contact to each other at least parts of their surfaces or side surfaces. Thereby, an alignment margin becomes unnecessary and the element is microscopically formed by the amount of the margin and an increase in the integration of the element becomes possible.

Description

[Detailed Description of the Invention] [Overview] Dynamic RAM (Random Access
The present invention relates to a semiconductor device and a manufacturing method thereof that allow for high integration of memory cells in memory (memory), and provides a semiconductor device and a manufacturing method thereof in which a trench capacitor can be formed close to a word line and high integration can be achieved through a miniaturized structure. The substrate has a trench capacitor and trench isolation, and the word line or the insulating film on the side surface of the word line and the trench for the capacitor are in contact with each other on at least part of the surface or side surface. a step of forming trench isolation on a substrate; a step of forming a word line and an insulating film on the side surfaces of the word line; and forming a trench for a capacitor.

[Industrial application field]

The present invention utilizes a dynamic RAM (Random A
The present invention relates to a semiconductor device and a method for manufacturing the same that achieves high integration of memory cells in memory cells (access memory).

[Conventional technology]

Conventionally, in order to increase the memory capacity per chip,
A semiconductor dynamic RAM is known in which each memory cell includes one transistor and one capacitor. In the field of dynamic RAM, it is necessary to miniaturize the isolation (element separation) of storage cells as the integration becomes higher, and the conventional selective oxidation (LOGO)
S (Local 0xi-dation of 5i
In place of the buried oxidation structure using the licon) method, trench type element isolation is now being used in which a trench is formed and an insulator is buried. On the other hand, the capacitors of the storage cells of the dynamic RAM are also formed on a conventional plane. Since the Brehner type requires a large area, trench type capacitors are now being manufactured in which a groove is formed. When forming a memory cell of a dynamic RAM using these trench type isolations and trench type capacitors, isolation is first formed, and then a capacitor region is formed in a portion separated from the isolation pattern. .

FIG. 6 is a plan view showing the configuration of a conventional memory cell. In the same figure, 1 is an element region, 2 is an isolation region in which a groove for isolation of elements is formed, and 3 is a word line formed in parallel in the vertical direction. A bit line (not shown) is formed perpendicularly to the word line 3. Then, a trench capacitor region 4 is formed at a predetermined distance from the isolation region 2 and the word line 3. In such a memory cell configuration, as shown in the figure, the isolation region 2 and the trench capacitor region 4 must be separated by a dimension a in the vertical direction as an alignment margin for each pattern, and the distance is increased by that amount. There was a problem that miniaturization of the element could not be achieved.

In order to solve the above problems, Fig. 7+8) and (b)
As shown in FIG. 2, a method has been proposed in which a trench capacitor region 5 is formed in self-alignment (self-alignment) with an isolation region 2, and a capacitor is formed on the side wall of the isolation region 2. That is, in FIG. 5(a), a capacitor trench is formed with a self-alignment line using a common etch mask pattern 6, which indicates adjacent trench capacitor regions 5 with dotted lines, and in FIG. 2(b), each trench capacitor region 5 is Capacitor trenches are formed in self-aligned lines using an etch mask pattern 7 shown in dotted lines every 5 minutes. With such a structure of the memory cell, the portion where the isolation region 2 and the trench capacitor region 5 are in contact can be formed by a self-alignment line, so that the element can be made into an AM structure by the amount of alignment margin of the pattern.

[Problem that the invention seeks to solve]

However, in the structure of the memory cell as described above, the portion where the isolation region 2 and the trench capacitor region 5 contact can be formed by a self-line, but the end of the word line 3 and the end of the etch mask pattern 6. Figures (al and (
As shown in b), there is a problem in that a dimension l is required for alignment, and it is not possible to miniaturize by that amount.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor device in which a trench capacitor can be formed close to a word line and a high degree of integration can be achieved through a miniaturized structure, and a method for manufacturing the same.

[Means for solving problems]

The above-mentioned problem is characterized in that the substrate has a trench capacitor and trench isolation, and the word line or the insulating film on the side surface of the word line and the trench for the capacitor are in contact with each other on at least part of the surface or side surface. a step of forming trench isolation on a substrate; a step of forming a word line and an insulating film on the side surfaces of the word line; The present invention is solved by a method for manufacturing a semiconductor device, which includes the steps of: forming a trench for a capacitor;

(Function) That is, in the present invention, since the insulating film on the side surface of the word line and the trench for the capacitor are in contact with each other on at least part of the surface or side surface, there is no need for alignment margin, and the element can be miniaturized accordingly. High integration is achieved.

In addition, in the present invention, trenches for capacitors are formed by etching the substrate with self-line using trench isolation and the insulating film on the side surfaces of the word lines as masks, so alignment margins are unnecessary, and the elements can be miniaturized accordingly. ,
High integration is achieved.

[Implementation L chest]

Embodiments of the present invention will be specifically described below with reference to the drawings.

FIG. 1 shows a dynamic RAM according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view of a memory cell portion of FIG. Description of this example 1. a
As shown in the plan view of FIG.
) is formed at the intersection with a bit line (not shown), and a capacitor trench portion shown by diagonal lines is formed in contact with the word line, and is of an oven bit line type. FIG. 1 is an enlarged sectional view taken along the line A--A in FIG. 4.

In FIG. 1, 11 is a P-type silicon (Si) substrate;
2 is an oxide B'J (5i02 film) for isolation between elements formed in an isolation trench, 13 is a P-type channel stopper, 14 is a word line made of polysilicon + W*WSI, etc., 15 is an insulating film, 16A and 16B are N+ type source/drain regions, 17 is a capacitor plate (capacitor upper electrode) formed in a trench for a capacitor between the oxide film 12 for element isolation and the insulating film 15 on the side of the word line 14, and 18 is a capacitor for the capacitor. The insulating film L9 is a glabellar insulating film made of polysilicate glass (PSG), 20 is a contact window, 21 is an aluminum electrode constituting a bit line, and 22 is a protective film made of PSG. That is, it has a trench capacitor and trench isolation, and has a gate insulating film 1 on the side surface of the word line 14.
5 and the capacitor trench are in contact with each other on at least part of the surface or side surfaces. In the memory cell of the dynamic RAM having this structure, as shown in FIG. The circuit configuration is such that the gate electrode is connected to the bit line, the drain electrode is connected to the bit line, and the source electrode is connected to the capacitor 24.

Dynamic I of such a structure? In the AM memory cell, the insulating film 15 on the side surface of the word line 14 and the capacitor trench are in contact with each other on at least part of the surface or side surface, so alignment margin is unnecessary.
The elements can be miniaturized to that extent, and high integration can be achieved.

In addition, in such a structure, when the cell area is the same, the area of the capacitor can be increased, and the reliability of the memory cell can be improved by designing with a margin.

Next, the method for manufacturing the trench isolation and trench capacitor portions of the memory cell having the above structure will be mainly described.

FIGS. 2(a) to 2(f) are sectional views showing the manufacturing process of a memory cell of a dynamic RAM according to an embodiment of the present invention.

Note that parts corresponding to those in FIG. 1 are denoted by the same reference numerals.

First, as shown in FIG. 2A, an isolation trench 25 is formed in a P-type silicon (Si) substrate 11.

Next, as shown in FIG. 1 (bl), an oxide film (5iOz film) 12 for element isolation is formed in the isolation trench 25 to an extent that it is slightly raised above the substrate 11.

Next, as shown in FIG.
A word line 14 made of polysilicon is patterned on a thermal oxide film (gate insulating film 15) made of 5i02 with a film thickness of approximately 0.000 nm.

Next, as shown in +d) of the same figure, the film thickness was increased to 2500°C at 800°C.
A silicon oxide film (SiO2 film) is deposited by vapor phase growth (CVD). Next, as shown in FIG. 8, the oxide film on the substrate 11 is removed by etching the oxide film on the plane, leaving the side surfaces intact. This makes the word line 14 5i0
It is formed in a shape surrounded by two films.

Next, as shown in FIG. 2F, after forming a resist film 26, an etching window 27 is formed between the centers of the insulating film 15 above the word line 14.

Next, as shown in FIG. 5(g), 5 iCI! was applied using the resist film 26 as a mask. 0.0 using 4/CR,2
Etching is performed to form grooves by RIE (reactive ion etching) under conditions of approximately 2 Torr and 500 W. As a result, the oxide film 15 portion is not etched,
A depth of 2 to 5 cm is formed between the oxide film 15 on the side surface of the word line 14 and the portion of the substrate 11 that is in contact with the side surface of the oxidized BIJJ 12 for element isolation.
A capacitor trench 28 of approximately μm size is formed by self-line.

A trench capacitor is formed by forming a capacitor insulating film 18, a capacitor plate 17, etc. as shown in FIG. 1 in the capacitor trench 28 formed by the above manufacturing process.

According to this method of manufacturing a memory cell, the word line 14
Since the capacitor trench 28 can be formed by self-line between the insulating film 15 on the side surface of the substrate 11 and the part of the substrate 11 in contact with the side surface of the oxide film 12 for element isolation, there is no need for alignment margins in both the vertical and horizontal directions. As a result, the elements can be miniaturized accordingly and high integration can be achieved.

3(a) to (C1) are sectional views showing the manufacturing process of a memory cell of a dynamic RAM according to another embodiment of the present invention.

After the same process as in Fig. 2 (al to (d)), Fig. 3 (a)
After forming the resist film 26, an etching window 27 including the side surface of the gate insulator 1!i!15 and the oxide film 12 is formed as shown in FIG.

Next, as shown in FIG. 3, the oxide film on the substrate 11 is removed using the resist film 26 as a mask.

Next, as shown in FIG. 3(C), similar to FIG. 2(g), etching is performed between the oxide film 15 on the side surface of the word line 14 and the portion of the substrate 11 in contact with the side surface of the oxide film 12 for element isolation. A capacitor trench 28 is formed by self-line.

According to such a method of manufacturing a memory cell, the elements can be miniaturized as shown in FIG. 2, and high integration can be achieved.

Note that, in the present invention, any structure is sufficient as long as the insulating film on the side surface of the word line and the trench for the capacitor are in contact with each other on at least part of the surface or side surface.

In addition, in the above embodiment, the gate insulating IJ15 is made of Si.
Although it is an O+ film, other nitride films (SilNm films) PS
G membrane or a combination thereof can be used.

Furthermore, although this embodiment uses an open bit line method, it can also be applied to a conventional fold-de-soto bit line method. In addition, in recent years, the conventional fall-default bit line method has a limit in the degree of integration, and devices have been proposed that allow each cell to be sensed using the oven bit line method even if the peripheral circuitry is changed. The present invention can be applied to.

〔Effect of the invention〕

As described above, according to the present invention, by forming capacitor trenches using word lines and self-aligned lines, trench capacitors can be formed close to word lines, and high integration can be achieved through miniaturization.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of the memory cell portion of the embodiment of the present invention, FIGS. 2(a) to (g) are sectional views of the manufacturing process of the memory cell of the embodiment of the present invention, and FIGS. 3(al to C) are 4 is a plan view of the memory cell portion of the embodiment of the present invention, FIG. 5 is an equivalent circuit diagram of the device shown in FIG. 1, and FIG. Plan view of the memory cell portion of the conventional example, FIG. 7(a)
, (b) are plan views of a memory cell portion of a conventional example. In the figure, 11 is a P-type silicon substrate, 12 is an oxide film, 13 is a P-type channel stopper, 14 is a word line, 15 is an insulating film, 16A and 16B are N1-type source/drain regions, 17
is a capacitor plate, 18 is an insulating film for the capacitor, 19 is an insulating film between the eyebrows, 20 is a contact window, 21 is an aluminum electrode, 22 is a protective film, 23 is a transistor, 24 is a capacitor, 25 is an isolation trench, 26 is a resist 27 is an etching window, and 28 is a capacitor trench. Patent Applicant: Fujitsu Ltd. Representative Patent Attorney Akira Kukimoto, Kon (Memory of the Kasako Yumi Kanse I Yumi, including the proboscis of Shiho, Figure 1) No.b company LD majesty town map 2nd figure
Front view Figure 3 Asawadan Monthly J Eiko 11's memory Nori Kado side view Figure 4 Figure 1 Force 11 should be on the same side Figure 5 Figure 5

Claims (2)

[Claims] (1) A semiconductor having a trench capacitor and trench isolation on a substrate, wherein a word line or an insulating film on the side surface of the word line and the trench for the capacitor are in contact with at least part of the surface or side surface. Device. (2) a step of forming trench isolation on the substrate; a step of forming an insulating film on the word line and the side surface of the word line; forming a capacitor trench with a self-line for the trench isolation and the insulating film on the side surface of the word line; A method for manufacturing a semiconductor device, comprising the step of forming a semiconductor device.