JPH0438144B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and in particular to a semiconductor memory device mainly used for dynamic random access memory (D-RAM) included in various information processing devices. The present invention relates to an improved structure of a transistor/single capacitor type memory cell for increasing the capacitor capacity and reducing the cell area.

The scale of the D-RAM is rapidly increasing, and along with this, the one-transistor/one-capacitor type memory cell that constitutes the D-RAM has also been significantly reduced in size.

A 1-transistor/1-capacitor type memory cell has a circuit configuration as shown in Figure 3.
Information is stored in capacitor C as a charge.

Then, when reading, transistor T is turned on.
and connect capacitor C and bit line BL,
The change in potential of the bit line BL caused by the accumulated charge is read out as information via the sense amplifier SA. (WL is a word line) Therefore, when the capacitor capacity decreases due to the reduction of memory cells, the change in potential of the bit line during reading becomes smaller, making reading information difficult and inaccurate, and reducing the reliability of information. descend.

Furthermore, when the capacitance of the capacitor decreases and the amount of charge stored as information decreases, inversion of information due to α rays becomes more likely to occur.

Therefore, there is a strong demand for the development of a means to increase capacitor capacity.

[Conventional technology]

FIG. 4 is a schematic side sectional view of a conventional one-transistor/one-capacitor memory cell.

In the figure, 1 is a p-type silicon substrate, 2 is an element isolation oxide film, 3 is an n ⁺ type drain region, 4 is an n ⁺ type source region which becomes the first capacitor electrode, 5
is a dielectric film, 6 is the first polycrystalline silicon layer P _A
7 is a first insulating film, 8 is a gate oxide film, 9 is a gate electrode made of a second polycrystalline silicon layer P _B , 10 is a second insulating film, 11 is aluminum The bit line is shown below.

The above normal type 1 transistor, 1 capacitor,
In the cell, only the upper part of the source region 4 is used as a capacitor as shown in the figure, so when the cell area is reduced, the capacitance is significantly reduced in proportion.

Therefore, a trench cell structure has been proposed as a method of increasing the effective area of the capacitor.

FIG. 5 is a schematic side sectional view showing a trench cell structure, in which 15 represents a trench, and other symbols indicate the same objects as in FIG. 4.

In this cell, a trench 15 is formed in advance in a region where the cell is to be formed by lithography by mask alignment, a source region 4 including the inner surface of the trench 15 is formed, and a second With the structure in which the capacitor electrode 6 is arranged, the effective area of the capacitor increases by the amount corresponding to the side surface of the groove 15, and the capacitor capacity can be increased.

However, when forming the trench cell, there is a margin d ₁ for the alignment error between the groove 15 and the capacitor electrode 6 and the capacitor electrode 6
Since it is necessary to consider the allowance dimension d ₂ for the positioning error between the gate electrode 9 and the gate electrode 9, there was a problem that the cell could not be miniaturized as desired.

Therefore, another structure for increasing the capacitor capacity is the stacked capacitor (stacked capacitor).
Capacitor (STC) type memory cells were provided.

FIG. 6 is a schematic side sectional view showing the structure of a conventional stacked capacitor type cell.

In the figure, 12a is a gate electrode made of the first polycrystalline silicon layer P _A , 12b is also a gate electrode (word line) of an adjacent memory cell,
13 is a first capacitor electrode made of a second polycrystalline silicon layer, 14 is a second capacitor electrode made of a third polycrystalline silicon layer, and other symbols indicate the same objects as in FIG. 4. .

As shown in the figure, in a stacked capacitor type cell, the upper part of the gate electrode 12a of the self-cell,
Another gate electrode extending from above the adjacent cell onto the device isolation oxide film, that is, the upper part of the adjacent word line 12b, is also used as a capacitor region, so compared to the conventional conventional memory cell, the same cell The capacitor capacity in terms of area can be increased about three times.

[Problem that the invention seeks to solve]

However, in the D-RAM, there is a demand for higher density and higher integration of memory cells, and we have provided a cell structure that can obtain a capacitance comparable to the current stacked capacitor type cell even if the cell area is further reduced. The problem arises that it has to be done.

[Means for solving problems]

The above problem can be solved by forming a groove-shaped impurity introduction region in which the periphery of the opening is defined by a gate electrode and an element isolation insulating film, and directly contacting the inner surface of the groove-shaped impurity introduction region, and a first capacitor electrode extending onto an adjacent gate electrode via an insulating film; a dielectric film formed on a surface of the first capacitor electrode; This is achieved by a stacked capacitor type semiconductor memory device according to the present invention having a second capacitor electrode covering the electrode.

[Effect]

That is, in the present invention, a groove-shaped source region is provided in the cell region in self-alignment with the gate electrode and the isolation region, and a stack-type capacitor is formed along the inner surface of the groove-shaped source region. Both ends extend above the gate electrode of the self cell and above the adjacent word line, thereby greatly increasing the effective area of the capacitor and at the same time reducing the cell area.

In this way, the reliability of information is ensured when the dynamic type memory is made even more dense and highly integrated.

〔Example〕

The present invention will be specifically explained below with reference to an embodiment shown in FIG.

FIG. 1 is a schematic plan view a and A-A showing an embodiment of a stacked capacitor type memory cell of the present invention.
Fig. 2 is a schematic sectional view b in the direction of arrows, and Figs. 2a to 2f are process sectional views showing the manufacturing method thereof.

The stacked capacitor type memory cell of the present invention has a structure as shown in FIG. 1, for example.

In the figure, 21 is a p-type silicon substrate, 22
23 is an element isolation oxide film, 23 is a gate oxide film, and 24 is an isolation oxide film.
a is a gate electrode made of the first polycrystalline silicon layer _PA , 24b is a gate electrode (word line) of an adjacent transistor also made of the first polycrystalline silicon layer PA, and 25 is silicon dioxide (SiO ₂ ).
26 is a gate electrode 24;
27 is a first capacitor electrode made of the second polycrystalline silicon layer P _B , and 28 is a groove with a depth of about 2000 Å, which is formed by self-alignment in a and the element isolation oxide film 22. n ⁺ type source region, 29 is a dielectric film made of SiO ₂ film etc. with a thickness of about 100 Å, 30 is the third layer of polycrystalline silicon layer
A second capacitor electrode made of P _C , 31 is a second capacitor electrode.
32 is an n ⁺ type drain region, 33 is a second insulating film made of phosphosilicate glass (PSG), 34 is a drain contact window, and 35 is a bit line made of aluminum, etc. .

The above structure is formed by the manufacturing method shown in FIGS. 2a to 2f.

That is, as shown in FIG. 2a, after forming an element isolation oxide film 22 on, for example, a p-type silicon substrate 21 as usual, a gate oxide film 2 with a thickness of about 300 Å is formed on the exposed silicon surface by thermal oxidation.
3 is formed, and then a first polycrystalline silicon layer P _A with a thickness of approximately 4000 Å is grown in a vapor phase on the substrate, and phosphorus is introduced at a high concentration by a gas diffusion method to form the first polycrystalline silicon layer P A. Gives conductivity to layer P _A.

Next, as shown in FIG. 2b, the first polycrystalline silicon layer P _A is patterned using a normal lithography technique to form gate electrodes 24a and 24b made of P _A , and the exposed gate oxide film is After removing 23, the surface of the gate electrodes 24a and 24b is coated with a thickness of, for example, 3000 Å by thermal oxidation.
A silicon oxide insulating film 25a is then formed. At this time, the thickness of the silicon oxide insulating film 25b formed on the single crystal silicon surface with low impurity concentration, that is, the surface of the p-type silicon substrate 21, is about 1/5 of that on the above P _A , that is, about 600 Å.

Next, as shown in FIG. 2c, a resist mask 42 is formed on the substrate to cover the drain formation region 41, and first the source formation region 43 is etched by reactive ion etching using methane trifluoride (CHF ₃ ). The silicon oxide insulating film 25b having a thickness of about 600 Å is removed. At this time, the exposed silicon oxide insulating film 25a on the gate electrode remains with a thickness of about 2400 Å.

Next, using the silicon oxide insulating film 25a on the gate electrode 24a and the element isolation oxide film 22 as masks, a reactive etching process is performed using an etching gas consisting of, for example, carbon tetrachloride (CCl ₄ ) + oxygen (O ₂ ).
The surface of the P-type silicon substrate 21 exposed by ion etching is selectively etched, and a substantially vertical trench with a depth of about 2 μm is formed in the source formation region 43 in self-alignment with the gate electrode 24a and the element isolation oxide film 22. A groove 26 having side surfaces is formed.

Next, as shown in FIG. 2d, a second polycrystalline silicon layer P _B with a thickness of about 3000 Å is grown on the substrate in a vapor phase, and arsenic (As ⁺ ), for example, is ion-implanted at a high concentration, and then The second polycrystalline silicon layer P _B is made conductive by heating at about 100° C. for a predetermined period of time.

At this time, arsenic is diffused into the surface of the groove 26 in a solid phase to form an n ⁺ type source region 28 having a depth of about 2000 Å on the surface of the groove 26.

Next, as shown in FIG. 2e, the second polycrystalline silicon layer P _B is patterned using a normal lithography technique to form the gate electrode 24a of the self cell and the adjacent word line 24.
A first capacitor electrode 27 extending on the substrate is formed, and then a silicon dioxide dielectric film 29 with a thickness of, for example, about 100 Å is formed on the surface of the first capacitor electrode 27 by thermal oxidation, and then a silicon dioxide dielectric film 29 is formed on the substrate. Then, a third polycrystalline silicon layer _PC with a thickness of approximately 3000 Å is grown in a vapor phase, and then phosphorus is introduced at a high concentration into the third polycrystalline silicon layer _PC by a method such as gas diffusion to make it conductive. The second capacitor electrode 30
Nasu.

Next, as shown in FIG. 2f, an opening 31 is formed in the second capacitor electrode 30 by a normal lithography technique to expose the upper part of the drain formation region 41 including its neighboring region;
Arsenic (As ⁺ ) is ion-implanted at a high concentration using the capacitor electrode 30 and the gate electrode 24a exposed in the opening 31 as a mask, and a predetermined heat treatment is performed to form an n ⁺ type drain region 32.

Thereafter, formation of a phosphosilicate glass insulating film, formation of wiring contact windows, formation of wiring, etc. are carried out as usual to complete a one-transistor, one-capacitor type memory cell having a stacked structure as shown in FIG.

As described in the above embodiment, in the structure of the present invention, the groove of the source region on which the capacitor is formed is formed in self-alignment with the gate electrode and the element isolation insulating film. There is no need to provide alignment margin between the two.

Further, since the distance between the gate electrode and the capacitor electrode is determined by the thickness of the insulating film formed on the gate electrode, there is no need to consider alignment margins as in the case of mask alignment, and the distance can be significantly shortened.

On the other hand, in the structure of the present invention, as shown in the embodiment, the effective area of the capacitor is increased by the groove, and furthermore, the upper part of the gate electrode of the self cell and the upper part of the adjacent word line are used as the capacitor region, so that the effective area of the capacitor is increased. The capacitor capacity is significantly increased, and a capacitor capacity about 5 to 6 times larger than that of a conventional normal cell can be obtained.

Note that the structure of the present invention is also applicable to memory cells of opposite conductivity types.

The capacitor electrode may be formed of a high melting point metal silicide such as molybdenum silicide (MoSi ₂ ).

Furthermore, silicon nitride (Si ₃ N ₄ ) or the like is also used for the dielectric film.

〔Effect of the invention〕

As described above, in the stacked capacitor type memory cell of the present invention, the cell area can be reduced compared to the conventional cell area, and even when the cell area is reduced, a large capacitor capacity can be secured.

Therefore, according to the present invention, it is possible to further increase the density and integration of semiconductor memory devices such as D-RAM without reducing the reliability of information.

[Brief explanation of drawings]

FIG. 1 is a schematic plan view a and A-A showing an embodiment of a stacked capacitor type memory cell of the present invention.
A schematic cross-sectional view b in the direction of arrows, FIGS. 2 a to f are process cross-sectional views showing the manufacturing method, and FIG.
Equivalent circuit diagram of 1-capacitor type memory cell, 4th
The figure is a schematic side sectional view of a conventional conventional one-transistor/one-capacitor type memory cell, FIG. 5 is a schematic side sectional view of a trench cell, and FIG. 6 is a schematic side sectional view of a conventional stacked capacitor type cell. It is. In the figure, 21 is a p-type silicon substrate, 22 is a field oxide film, 23 is a gate oxide film, and 24a
and 24b is a gate electrode, 25 is a first insulating film,
26 is a groove, 27 is a first capacitor electrode, and 28 is a groove.
n ⁺ type source region, 29 a dielectric film, 30 a second
31 is a window, 32 is an n ⁺ type drain region, 33 is a second insulating film, 34 is a drain contact window, 35 is a bit line, P _A is the first polycrystalline silicon layer, P _B is the second layer The third polycrystalline silicon layer, P _C is the third polycrystalline silicon layer,
shows.

Claims (1)

[Claims] 1. A groove-shaped impurity introduction region in which the periphery of the opening is defined by a gate electrode and an element isolation insulating film, and a groove-shaped impurity introduction region that is in direct contact with the inner surface of the groove-shaped impurity introduction region and adjacent through an insulating film. a first capacitor electrode extending over the gate electrode, a dielectric film formed on the surface of the first capacitor electrode, and a second capacitor electrode covering the first capacitor electrode via the dielectric film. 1. A semiconductor memory device comprising: a capacitor electrode;