JPH05110075A - Insulated gate type field effect transistor - Google Patents

Abstract

PURPOSE:To effectively utilize the surface of a substrate and to dispense with a channel stopper by a method wherein an electrode formed on a drain diffusion layer is led outside striding over an interlayer insulating film formed on a gate region sandwiched between a drain diffusion layer and a source diffusion layer. CONSTITUTION:A drain electrode 7 is led outside from the upside of a ring- shaped gate electrode 6 through a multilayer interconnection structure which uses an interlayer insulating film 5 where an N<+>-type source diffusion layer 2 is formed around a gate region which fully surrounds an N<+>-type drain diffusion layer 9. By this setup, the gate region is fully surrounded with the N<+>-type source region 2, so that the source electrode 4 may be partially disconnected not, fully surrounding the gate region. Therefore, a channel stopper high concentration diffusion layer required for the disconnected part of a conventional ring-shaped gate can be dispensed with.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate field effect transistor.

[0002]

2. Description of the Related Art Regarding a conventional insulated gate field effect transistor, a plan view of FIG.
It will be described with reference to FIGS. 3B, 3C, and 3D, which are cross-sectional views taken along lines DF.

Conventionally, it was not possible to form the gate region in an annular shape. The gate region is interrupted at the portion where the drain electrode 7 connected to the drain diffusion layer 9 is drawn out.

Further, in order to suppress the leak current in the region where the gate region is interrupted, a channel stopper 8 made of a P ⁺ type diffusion layer is formed.

[0005]

In the conventional insulated gate field effect transistor, since the gate region cannot be formed in the portion where the drain electrode is pulled out from the drain diffusion layer, the current capacity is reduced accordingly. Further, a channel stopper made of a high-concentration diffusion layer for suppressing a leak current is required in a region where the annular gate region is interrupted. There are problems that the chip area is increased due to the formation of the high-concentration diffusion layer and that the number of PR steps is increased by one.

[0006]

In an insulated gate field effect transistor of the present invention, a drain diffusion layer of one conductivity type and an annular source diffusion layer surrounding the drain diffusion layer are formed on one main surface of a semiconductor substrate. An electrode formed on the drain diffusion layer is extended outside the source diffusion layer across an interlayer insulating film formed on the gate region sandwiched between the drain diffusion layer and the source diffusion layer. It is a thing.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention is shown in a plan view of FIG. 1 (a) and an AB sectional view of FIG. 1 (b), and its C.
The description will be made with reference to FIG. 1C which is a cross-sectional view taken along the line -D and FIG. 1D which is a cross-sectional view taken along the line EF.

An N ⁺ type source diffusion layer 2 is formed around a gate region that completely surrounds the N ⁺ type drain diffusion layer 9. Due to the multilayer wiring structure using the interlayer insulating film 5, the drain electrode 7 is drawn out from above the ring-shaped gate electrode 6.

Since the N ⁺ -type source diffusion layer 2 completely surrounds the gate region, the source electrode 4 does not completely surround the gate region and may be partially interrupted.

Next, a second embodiment of the present invention will be described with reference to FIG.
FIG. 2 is a plan view of (a) and a cross-sectional view taken along the line AB.
2B is a sectional view taken along the line C-D of FIG.
It will be described with reference to FIG.

A circular gate structure is used in order to effectively utilize the surface of the substrate and to improve the breakdown voltage by eliminating the electric field concentration in the gate region.

An N ⁺ type source diffusion layer 2 is formed around a gate region which completely surrounds the N ⁺ type drain diffusion layer 9. Due to the multilayer wiring structure using the interlayer insulating film 5, the drain electrode 7 is drawn out from above the ring-shaped gate electrode 6.

Also in this embodiment, since the N ⁺ type source diffusion layer 2 completely surrounds the gate region, the source electrode 4
Does not have to completely surround the gate region and may be partially interrupted.

[0014]

The drain diffusion layer is completely surrounded by the gate region, and the gate region is completely surrounded by the source diffusion layer. Further, the drain electrode is drawn out to the outside across the interlayer insulating film and across the gate region.

As a result, the surface of the substrate is effectively used, and the channel stopper made of the high concentration diffusion layer is not required. For example, in an annular gate region having a radius of 15 μm, the gate width is L _g1 = 2 × 3.14 × 15 = 94.
While it is 2 μm, in the conventional structure, about 20 μm is required for the extraction portion, so that L _g2 = 94.2-20.0 = 7.
It becomes 4.2 μm. Even if the chip area is the same, the gate width can be only 80% of that of the present invention in the prior art.

Further, the high-concentration diffusion layer for the channel stopper, which is required in the conventional portion where the annular gate is interrupted, becomes unnecessary. Conventionally, if the channel stopper is formed independently without any process that can be used in common, one step is not required in the present invention.

[Brief description of drawings]

FIG. 1A is a plan view showing a first embodiment of the present invention. (B) is an AB sectional view of (a). (C) is a CD sectional view of (a). (D) is EF of (a)
FIG.

FIG. 2A is a plan view showing a second embodiment of the present invention. (B) is an AB sectional view of (a). (C) is a CD sectional view of (a).

FIG. 3A is a plan view showing a conventional insulated gate field effect transistor. (B) is an AB sectional view of (a). (C) is a CD sectional view of (a).
(D) is an EF sectional view of (a).

[Explanation of symbols]

1 P ⁻ type semiconductor substrate 2 N ⁺ type source diffusion layer 3 oxide film 4 source electrode 5 interlayer insulating film 6 gate electrode 7 drain electrode 8 P ⁺ type diffusion layer (channel stopper) 9 N ⁺ type drain diffusion layer

Claims (1)

[Claims] 1. A drain diffusion layer of one conductivity type and an annular source diffusion layer surrounding the drain diffusion layer are formed on one main surface of a semiconductor substrate, and an electrode formed on the drain diffusion layer is the drain diffusion layer. And an insulated gate field effect transistor which is drawn out of the source diffusion layer across an interlayer insulating film formed on the gate region sandwiched between the source diffusion layers.