JPH0964344A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce semiconductor chip area and cost, by forming a first diffusion layer in the inside, and constituting, around it, an insulating film having a ring type pattern form, a second diffusion layer, a gate electrode having a half ring type pattern form which is cut off by a part of the insulating film, etc. SOLUTION: An N-well layer 1 is formed on the surface of a P-type silicon substrate. A low concentration drain diffusion layer 2 as a second diffusion layer whose outer peripheral form is octagonal is formed in the central region of the N-well layer 1. A ring type field insulating film 3a and a leading-out insulating film 3b are formed. A high concentration drain diffusion layer 5 as a first P-type diffusion layer having the same form as the ring type field insulating film 3a is formed inside the ring type field insulating film 3a. A gate electrode 4 of a half ring type which is cut off by the field insulating film 3b is formed outside the ring type field insulating film 3a. A drain electrode 8 is connected with the high concentration drain diffusion layer 5 through a drain contact hole 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, the present invention relates to a high breakdown voltage MOSFET that can be easily integrated into a CMOS semiconductor device.

[0002]

2. Description of the Related Art In semiconductor devices, their applications have been diversified along with their high integration and high speed.
Then, a CM for a general logic circuit is provided on the same semiconductor chip.
A large-scale semiconductor device in which an OSFET and a high breakdown voltage MOSFET are arranged in parallel has been put into practical use. For example, in a semiconductor device used for controlling a fluorescent display tube, a high breakdown voltage MOSFE is provided in a peripheral circuit connected to an output terminal from a semiconductor chip to the outside.
The high withstand voltage MOS is used inside the semiconductor chip.
C which constitutes a high voltage integrated circuit of low voltage operation for controlling FET
A MOSFET is formed. Then, in this case, a high voltage is applied to the drain of the high breakdown voltage MOSFET.

Conventionally, in the formation of such a high breakdown voltage MOSFET, the structure, dimensions, manufacturing method, etc. of the device are designed mainly with the following three points in mind.

That is, (1) high breakdown voltage of the junction of the diffusion layer forming the drain (2) prevention of dielectric breakdown between gate and drain (3) prevention of inversion of high breakdown voltage MOSFET channel portion by drain voltage High breakdown voltage MO used in semiconductor integrated circuits
The structure of the SFET will be described with reference to FIG. Here, FIG. 5A shows a P-channel type high breakdown voltage MOSFET.
FIG. 5B is a plan view of FIG. 5A, and FIG.
It is sectional drawing cut | disconnected by -B '.

As shown in FIGS. 5A and 5B, an N well layer 102 is formed in a predetermined region of a P type silicon substrate 101. Then, a P well layer is formed inside the N well layer 102 to form a low concentration drain diffusion layer 103. Further, field insulating films 104 and 104a are selectively formed on the surface of the silicon substrate on which such a well layer is formed.

Next, after forming the gate insulating film 105 of the high breakdown voltage MOSFET, a gate electrode 106 is provided. Then, a high-concentration drain diffusion layer 107 and a source diffusion layer 108 having a P-type conductivity are formed. An interlayer insulating film 109 that covers the field insulating films 104 and 104a, the gate electrode 106, the high-concentration drain diffusion layer 107, and the source diffusion layer 108 is formed.

Then, a drain electrode 111 connected to the high concentration drain diffusion layer 107 through the drain contact hole 110 and a source electrode 113 connected to the source diffusion layer 108 through the source contact hole 112 are formed to form a conventional P-channel type high breakdown voltage. MOSFET is completed.

In such a structure, the drain region is composed of the low concentration drain diffusion layer 103 and the high concentration drain diffusion layer 107 described above. Therefore, the junction of the drain region is formed in the junction region of the N well layer 102 and the low concentration drain diffusion layer 103. Then, when a negative high voltage such as −30 V is applied to the drain electrode 111,
Since the impurity concentration of the N well layer 102 and the low concentration drain diffusion layer 103 described above is low, the depletion layer extends in both directions. For this reason, the breakdown voltage of the junction of the diffusion layer is improved to withstand the high voltage described above, and the requirement (1) described above is satisfied.

A field insulating film 104a is formed between the gate electrode 106 and the low concentration drain diffusion layer 103. Usually, the field insulating film 104a is thick and does not cause dielectric breakdown by the high voltage applied to the gate electrode 106 and the drain electrode 111. That is, the requirement (2) described above is also satisfied.

As can be seen from the plan view of FIG. 5A, the gate electrode 106, the drain electrode 111 and the source electrode 11 are formed.
3 are both arranged in parallel. That is, in this structure, the drain electrode 111 does not intersect with the gate electrode 106 via the insulating film. That is, the drain electrode 111 is not provided above the channel region of the high breakdown voltage MOSFET. In this way, the requirement (3) described above is also satisfied.

[0011]

Such a high breakdown voltage MO
In semiconductor devices equipped with SFET, depending on the application,
For example, a large output current is required in the case of the above-described control of the fluorescent display tube, so that it is required to improve the driving capability thereof. In such a case, in the high breakdown voltage MOSFET described in the related art, the gate width of the MOSFET increases, and it becomes difficult to arrange these in the semiconductor chip.

Alternatively, in order to increase the driving capability, a plurality of high breakdown voltage MOSFETs are electrically connected in parallel, but the area occupied by the entire high breakdown voltage MOSFETs increases, which causes an increase in the semiconductor chip area. .

An object of the present invention is to solve the above-mentioned problems and to provide a semiconductor device equipped with a high breakdown voltage MOSFET in which the semiconductor chip area is reduced and the cost can be easily reduced.

[0014]

To this end, a semiconductor device according to the present invention has a first conductivity type first diffusion layer formed in a predetermined region of a semiconductor substrate and the first diffusion layer as an inner side. A thick insulating film formed in the periphery and having an annular pattern shape, and a second diffusion layer of the same conductivity type that is formed on the surface of the semiconductor substrate below the thick insulating film and has a lower impurity concentration than the first diffusion layer. The first diffusion layer and the second diffusion layer are used as drain regions, and the thin insulating film and the thick insulating film on the semiconductor substrate formed outside the thick insulating film pattern are formed into a gate insulating film. A semiconductive thin film formed on the gate insulating film and cut in a part of the thick insulating film and having a semi-annular pattern as a gate electrode, and formed outside the thick insulating film pattern with the gate electrode interposed therebetween. The same conductivity type of the third The high-voltage M to the goldenrod as a source region
Equipped with OSFET.

In this semiconductor device, the drain electrode that is electrically connected to the first diffusion layer and is drawn out to the outside of the thick insulating film pattern is disposed on the interlayer insulating film on the cut gate electrode, It is formed so as not to cross the gate electrode through the interlayer insulating film.

Alternatively, in this semiconductor device, a plurality of the high breakdown voltage MOSFETs are electrically connected in parallel and mounted.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a plan view of a high breakdown voltage MOSFET showing an embodiment of the present invention. As shown in FIG. 1, an N well layer 1 is provided in a predetermined region on the surface of a silicon substrate having a P conductivity type. Then, the low concentration drain diffusion layer 2 is formed in the central region of the N well layer 1. Here, the outer peripheral shape of the low concentration drain diffusion layer 2 is illustrated as an octagon, but this shape may be circular or other polygonal shape.

Then, the field insulating film 3 is formed.
Here, a part of the field insulating film 3 is formed in a ring shape. That is, the annular field insulating film 3a is provided so as to be located inside the low concentration drain diffusion layer 2 described above. Further, a lead field insulating film 3b is formed on a part of the field insulating film 3. This is connected to the annular field insulating film 3a as shown in FIG.

The gate electrode 4 of the high breakdown voltage MOSFET has a semi-annular shape as shown in FIG. 1 and covers the outer peripheral region of the annular field insulating film 3a. Then, the shape becomes an open shape on the region of the extraction field insulating film 3b described above. In FIG. 1, the gate electrode 4 is illustrated as an octagon, but this shape may be designed according to the shape of the outer periphery of the low concentration drain diffusion layer 2 described above.

Then, the above-mentioned annular field insulating film 3 is formed.
In the inside of a, the high-concentration drain diffusion layer 5 having a P-type conductivity is formed.
To form Here, the shape of the high-concentration drain diffusion layer 5 is the same as the shape of the annular field insulating film 3a described above. Then, the source diffusion layer 6 is provided in the silicon active region other than the region where the gate electrode 4 is formed, which is the region surrounded by the field insulating film 3. Here, the conductivity type of the source diffusion layer 6 is also P-type.

A drain electrode 8 is electrically connected to the high-concentration drain diffusion layer 5 through the drain contact hole 7. Then, as shown in FIG. 1, the drain electrode 8 is arranged on a part of the annular field insulating film 3a and the surface of the inter-layer insulating film on the extraction field insulating film 3b. Further, the source electrode 10 is electrically connected to the source diffusion layer 6 through the source contact hole 9. As described above, the high breakdown voltage MOSFET of the present invention is formed.

Next, the cross-sectional structure of the high breakdown voltage MOSFET of the present invention will be described and the manufacturing method thereof will be described with reference to FIGS. Here, FIGS. 2 and 3 are cross-sectional views taken along the lines AB and CD shown in FIG. 1, respectively.

As shown in FIG. 2, an N well layer 1 is formed in a predetermined region on the surface of a silicon substrate 11 having a P type conductivity and an impurity concentration of 10 ¹⁵ atoms / cm ³ . Where this N
The well layer 1 is formed by ion implantation of phosphorus impurities and subsequent heat treatment. This phosphorus impurity ion implantation has an implantation energy of 150 keV and a dose of 1 × 10 ^13.
/ Cm ^{2 It} is performed under the condition. The final depth of the N well layer is about 10 μm, and the concentration of phosphorus impurities is 10 ¹⁶
It is about atoms / cm ³ .

Next, the low concentration drain diffusion layer 2 is formed. Here, the low concentration drain diffusion layer 2 is formed by ion implantation of boron impurities and subsequent heat treatment. This boron impurity ion implantation has an implantation energy of 100 k.
eV, and the conditions are such that the dose amount is 1.5 × 10 ¹³ / cm ² . The final depth of the low-concentration drain diffusion layer 2 is about 3 μm, and the concentration of boron impurities is about 10 ¹⁷ atoms / cm ³ .

After this, the field insulating film 3 is formed. Further, an annular field insulating film 3a is formed in the low concentration drain diffusion layer 2. Here, these field insulating films are formed by a known selective oxidation method on the surface of the silicon substrate, and the film thickness thereof is set to about 600 nm.

Next, a silicon oxide film having a film thickness of about 15 nm is formed and a gate insulating film 12 is provided. Then, the gate electrode 4 is formed so that a part thereof covers the annular field insulating film 3a. Here, the gate electrode 4 is formed of tungsten polycide. After doing so, the high concentration drain diffusion layer 5 and the source diffusion layer 6 are formed. These diffusion layers are formed by ion implantation of BF ₂ and heat treatment. Here, the implantation energy is about 70 keV and the dose amount is about 10 ¹⁵ / cm ² . In this way, the depth of these diffusion layers is set to about 1 μm.

Next, the interlayer insulating film 13 is formed of a silicon oxide film having a film thickness of about 500 nm. Here, this silicon oxide film is deposited by a known chemical vapor deposition (CVD) method. Then, the interlayer insulating film 1 on the high-concentration drain diffusion layer 5
3 and a contact hole is formed in the interlayer insulating film 13 on the source diffusion layer 6, and the drain electrode 8 electrically connected to the high-concentration drain diffusion layer 5 and the source electrode 10 electrically connected to the source diffusion layer 6 are formed. In this way, the high breakdown voltage MOSFET of the present invention is formed.

Next, the structure of the present invention will be described with reference to FIG. As shown in FIG. 3, the N well layer 1 is formed on the surface of the silicon substrate 11. As described with reference to FIG. 2, the impurity concentration of this N well layer is 1 × 10 ¹⁶ atoms / cm ³ . Then, the channel prevention layer 1a is formed on the surface portion of the N well layer 1 in the boundary region with the above-mentioned extraction field insulating film 3b. Here, the phosphorus impurity concentration of the channel prevention layer 1a is set to about 5 × 10 ¹⁶ atoms / cm ³ . next,
The low concentration drain diffusion layer 2 is formed. Here, the depth of the diffusion layer is about 3 μm, and the impurity concentration thereof is about 10 ¹⁷ atoms / cm ³ . Then, the field insulating film 3 or the annular field insulating film 3a and the extraction field insulating film 3b are formed on the surface of the silicon substrate 11.

Next, the gate insulating film 12 is formed of a silicon oxide film.
Is provided. Then, the gate electrode 4 is formed. here,
The gate electrode 4 is made of tungsten polycide. After doing so, the high concentration drain diffusion layer 5 is formed. The depth of this diffusion layer is set to about 1 μm.

Next, the interlayer insulating film 13 is formed of a silicon oxide film having a film thickness of about 500 nm. Here, this silicon oxide film is deposited by a known CVD method. Then, a contact hole is formed in the interlayer insulating film 13 on the high concentration drain diffusion layer 5, and a drain electrode 8a electrically connected to the high concentration drain diffusion layer 5 is formed. In this way, the high breakdown voltage MOSFET of the present invention is formed.

As described above with reference to the plan view and the sectional views in the two directions, in the high breakdown voltage MOSFET of the present invention, the high concentration drain diffusion is performed on the surface of the silicon substrate surrounded by the annular field insulating film having an annular closed shape. A layer is formed. The channel region is formed along the outer peripheral region of the annular field insulating film. Further, the diffusion layer serving as the source is formed outside the channel region. For this reason, for example, a high breakdown voltage M having a gate electrode width of 35 μm and a driving force of 30 mA current necessary for controlling a fluorescent display tube.
In the case of the OSFET, the area occupied by this high breakdown voltage MOSFET is reduced to about 80% as compared with the conventional case.

In the structure of the present invention, the drain electrode 8a is not provided in the upper layer portion of the gate electrode 4 when the drain electrode is drawn out. Then, similarly to the conventional technique, the above-described conditions (1), (2) and (3) are satisfied.

Next, referring to FIG. 4, a high breakdown voltage MOS having the structure of the present invention.
An embodiment in which a plurality of FETs are connected in parallel will be briefly described. Here, for the sake of simplicity, the description of the low-concentration drain diffusion layer is omitted.

As shown in FIG. 4, a plurality of high breakdown voltage MOSFs are provided.
An N well layer 21 commonly used for ET is formed.
Then, the field insulating film 22 is formed, and further the gate electrode wiring 23 connected to the plurality of gate electrodes is formed.

Then, the high concentration drain diffusion layer 24 and the source diffusion layer 25 are formed. Also, each high withstand voltage M
In the high concentration drain diffusion layer 24 formed in the OSFET,
A drain electrode wiring 27 that is electrically connected through the drain contact hole 26 is formed. Further, a source electrode wiring 29 electrically connected to the source diffusion layer 25 through the source contact hole 28 is formed.

In this way, the high breakdown voltage M of the structure of the present invention is
By connecting a plurality of OSFETs in parallel, it becomes possible to mount high-voltage MOSFETs having a higher driving capability than in the conventional case in a high density in a semiconductor chip.

In the embodiment of the invention described above, the high breakdown voltage MO
Although the case where the SFET is a P-channel type has been described,
It should be noted that in the case of the channel type, it can be similarly formed by reversing the conductivity type.

Further, in this embodiment, when the source contact holes are formed outside the semi-annular gate electrode at equal intervals and the source diffusion layer is electrically connected to the source electrode, the electrical resistance on the source side is reduced and the It should be noted that the driving capability of the breakdown voltage MOSFET is further improved.

[0039]

In the semiconductor device of the present invention, the high withstand voltage MOSFET to be mounted is a first conductivity type first diffusion layer formed in a predetermined region of the semiconductor substrate, and the first diffusion layer is inside. A pattern-shaped thick insulating film which is formed around and has a certain width and is closed, and a second insulating layer which is formed on the surface of the semiconductor substrate below the thick insulating film and has a lower impurity concentration than the first diffusion layer and which has the same conductivity type. A thin insulating film on the semiconductor substrate and a thick insulating film formed outside the thick insulating film pattern, the first insulating layer and the second diffusing layer serving as drain regions. As a gate insulating film, a conductor thin film pattern formed on the gate insulating film and cut by a part of the thick insulating film as a gate electrode, and formed outside the thick insulating film pattern with the gate electrode interposed therebetween. Same conductivity type The diffusion layer and the source region.

For this reason, the occupied area of the high breakdown voltage MOSFET is reduced and the driving capability thereof is significantly improved. Then, the semiconductor chip area of the semiconductor device of the present invention is reduced, and the cost can be easily reduced.

[Brief description of drawings]

FIG. 1 is a plan view of a high breakdown voltage MOSFET for explaining the present invention.

FIG. 2 is a cross-sectional view of a high breakdown voltage MOSFET for explaining the present invention.

FIG. 3 is a cross-sectional view of a high breakdown voltage MOSFET for explaining the present invention.

FIG. 4 is a plan view of parallel high breakdown voltage MOSFETs of the present invention.

FIG. 5: High breakdown voltage MOSFET for explaining a conventional technique
FIG.

[Explanation of symbols]

 1, 21, 102 N well layer 1a Channel prevention layer 2, 103 Low concentration drain diffusion layer 3, 22, 104, 104a Field insulating film 3a Annular field insulating film 3b Extraction field insulating film 4, 106 Gate electrode 5, 24, 107 High concentration drain diffusion layer 6,25,108 Source diffusion layer 7,26,110 Drain contact hole 8,111 Drain electrode 9,28,112 Source contact hole 10,113 Source electrode 11,101 Silicon substrate 12,105 Gate insulating film 13,109 Interlayer insulating film 23 Gate electrode wiring 27 Drain electrode wiring 29 Source electrode wiring

Claims (3)

[Claims] 1. A first conductivity type first diffusion layer formed in a predetermined region of a semiconductor substrate, and a thick insulating film formed around the first diffusion layer and having an annular pattern shape. A second diffusion layer formed on the surface of the semiconductor substrate below the thick insulating film and having a lower impurity concentration and the same conductivity type than the first diffusion layer, the first diffusion layer and the second diffusion layer. A diffusion layer as a drain region, a thin insulating film on the semiconductor substrate formed outside the thick insulating film pattern and the thick insulating film as a gate insulating film, and the thick insulating film formed on the gate insulating film. A conductive thin film having a semi-circular pattern shape cut by a part of the film is used as a gate electrode, and a third diffusion layer of the same conductivity type formed outside the thick insulating film pattern with the gate electrode interposed therebetween is used as a source. High-voltage MOSFET for the area A semiconductor device characterized by being mounted. 2. A drain electrode, which is electrically connected to the first diffusion layer and is drawn out to the outside of the thick insulating film pattern, is disposed on the cut gate electrode, and the gate is formed through an interlayer insulating film. The semiconductor device according to claim 1, wherein the semiconductor device is formed so as not to intersect the electrodes. 3. A plurality of the high breakdown voltage MOSFETs are electrically connected in parallel and mounted.
Alternatively, the semiconductor device according to claim 2.