JPS5965453A - Semiconductor device having multi-layer wiring - Google Patents

Abstract

PURPOSE:To make free the interface between an insulating film and semiconductor from influence of coupling in electricalfield due to the upper wiring layer by providing a plurality of wiring layers on the surface of a semiconductor substrate through an insulating film and setting the lower wiring layer to a potential lower than the inverted potential. CONSTITUTION:A thick silicon dioxide film 12 is formed on a silicon substrate 11 by selective oxidation method, source regions 13, 15, drain regions 14, 16 are formed by the selective diffusion method with such film used as the isolating region, and a first wiring layer 19 and a second wiring layer 20 of the conductive polycrystalline silicon are insulatingly formed on the silicon dioxide film 12 through an inter-layer insulating film 21. The first wiring layer 19 is placed in contact with the silicon substrate 11 so that it is in the same potential as the silicon substrate 11 and is kept at a voltage lower than the inverted voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to semiconductor integrated circuits, particularly to semiconductor devices having multilayer wiring widely used in MO8 integrated circuits.

Conventional configuration and its problems M(1)S integrated circuit (hereinafter referred to as MC)
In this case, the wiring connecting elements is formed in a multilayer structure,
Moreover, the wiring is often provided on a thick insulating film that separates the elements.

FIG. 1a is a plan view schematically showing the main parts of a normal hiUsIc, and the figure is a cross-sectional view taken along the line XX. As, on both sides of MQS) transistor source regions 3, 6
, drain regions 4, 6 are diffused and associated insulated gate electrodes 7, 8 are provided. Then, on the thick insulating film 2, a wiring layer 9 is provided using aluminum or conductive polycrystalline silicon.
is used for power supply or transmission lines for signal reception.

By the way, a conductive region called a channel layer, a so-called inversion layer, is easily induced directly under the thick insulating film 2, and this causes electrical coupling between pixel elements and causes signal leakage. A region 10, called a channel stop, is provided which prevents formation. This channel stopper 10 is formed, for example, when selectively forming the thick insulating film 9, in combination with a process in which high-concentration impurities that provide the same type of conductivity as the substrate silicon 1 are diffused and introduced. . However, if the function of the channel stopper 10 is insufficient, for example, if the impurity concentration in the region 10 is low, or if the insulating film 2 is insufficiently thick, a signal leak phenomenon may occur. For this reason, the tendency is to make the thickness of the insulating film 2 as thick as possible and to make the impurity concentration of the channel stopper 1o high. However, selection of such a tendency is not preferable because it increases the occupied area of the element isolation region or causes a decrease in the breakdown voltage characteristics of MO8I'C.

Purpose of the Invention The present invention aims to solve the problems seen in the above-mentioned conventional example, and mainly forms a wiring layer on the isolation region between the elements and creates an electric field at the interface between the insulating film and the semiconductor directly below. It is an object of the present invention to provide a semiconductor device having a multilayer wiring structure that does not have the influence of

Structure of the Invention The present invention provides a semiconductor device having a multilayer interconnection formed by providing a plurality of interconnection layers on the surface of a semiconductor substrate via an insulating film, and holding the lower interconnection layer at a lower potential than an inversion layer formation potential. By setting the lower wiring layer at a potential lower than the inversion potential, the influence of electric field coupling due to the upper wiring layer stacked thereon will not affect the interface between the insulating film and the semiconductor. The electrical characteristics of the semiconductor device are significantly stabilized.

DESCRIPTION OF THE EMBODIMENTS FIG. 2a schematically shows a plan view of an apparatus according to an embodiment of the present invention, and a sectional view taken along the line Y-Y in the figure. In this device, a thick silicon dioxide film 12 is formed on a predetermined portion of a silicon substrate 11 by selective oxidation, and this is used as an isolation region, and a source region 13.15 and a drain region 14.16 are formed on both sides of the film.
is formed by the usual selective diffusion method, and there is still an insulated gate electrode 17 between the source and drain related to them.
．． 18 are provided for each. Then, on the thick silicon dioxide film 12, a first wiring layer 19 and a second wiring layer 20 made of conductive polycrystalline silicon are provided so as to be insulated from each other via an interlayer insulating film 21. Reference numeral 19 has an electrode connection part that can be connected to the outside. In addition, in the same figure, 22 is a channel stopper, and its formation method is the same as that of the conventional example.

FIG. 3 shows the electrical characteristics of the device according to the present invention.
The horizontal axis (X-axis) represents the voltage Vi applied to the first wiring layer 19, and the vertical axis (Y-axis) represents the voltage at which the channel layer is formed by the voltage applied to the second wiring layer 20 (hereinafter referred to as (called reversal voltage)
It represents v■.

According to FIG. 3, when the voltage applied to the first wiring layer 19 is zero,
In other words, if vI=0, the inversion voltage Vn of the second wiring layer 2o is higher than the normal inversion voltage Vi caused by only the voltage Vl applied to the first wiring layer 19 due to the shielding effect of the first wiring layer 19. It can also be seen that the channel layer is not induced at a fairly high voltage 1. Furthermore, when the voltage vI applied to the first wiring layer 19 is increased sequentially from zero, the reversal voltage . As the voltage Vl applied to the first wiring layer 19 approaches its own inversion voltage Vi, the inversion voltage VB caused by the voltage applied to the second wiring layer 20 also decreases.

Note that even when the voltage applied to the first wiring layer 19 is a negative voltage, the inversion voltage Vn due to the voltage applied to the second wiring layer 20'
changes flatly at the level of ■I=○. According to experience, in the device of this embodiment, when the thickness of the thick silicon dioxide film 12 is 0.8 μm, the reversal voltage Vi due to the voltage applied to the first wiring layer 19 is the reference value for a leakage current of 1 μm. However, when the voltage V■ applied to the first wiring layer 19 is set to zero (VI-0), the inversion voltage vIl due to the voltage applied to the second wiring layer 20 becomes approximately 75V. A significant deterrent effect on channel layer formats was observed.

Furthermore, according to this embodiment, as is clear from FIG. If the voltage applied to the droplet is in a low range, the reversal voltage due to the voltage applied to the second wiring layer 20 can be sufficiently increased. Actually, the first wiring layer 19 is formed on the silicon substrate 11.
It is best to touch the silicon substrate 11 so that the potential is the same as that of the silicon substrate 11. If this is done, there is also the advantage that there is no need for a connecting part for applying external power.

As explained in more detail in the embodiments than the effects of the invention, according to the present invention, a plurality of wiring layers are provided on a thick insulating film serving as an insulating isolation region, and the lower wiring layer is connected to an inversion layer forming voltage, so-called inversion. Since the potential is held lower than the voltage, the voltage applied to the upper wiring layer can be increased to a voltage several times higher than the conventional inversion voltage. This is advantageous for high integration because a desired high inversion voltage can be ensured without increasing the thickness of the insulating isolation film formed by selective oxidation. Further, the process used can be a normal two-layer polycrystalline silicon process or a process for forming two-layer aluminum wiring, so no particularly complicated process is required.

Although the present invention has been exemplified as being effective as electrical wiring between transistors in MO3IC, it can also be applied to isolation regions between elements including resistors and capacitors.

[Brief explanation of drawings]

1A and 1B are a plan view and a sectional view of conventional electrode wiring formation, FIGS. 2A and 2B are a plan view and a sectional view of electrode wiring formation according to the present invention, and FIG. 3 is an apparatus according to the present invention. FIG. 11... Semiconductor substrate, 13.16... Source region, 14.16... Drain region, 17.1
8...Gate region, 12...Thick film oxide film region, 19...First wiring layer, 20...
・Second wiring layer, 21... Interlayer insulating film, 22...
...Channel stopper area.

Claims (1)

[Scope of Claim] A semiconductor device having multilayer wiring held at a potential lower than a forming potential. (2) A semiconductor device having a multilayer wiring according to claim 1, wherein the lower wiring layer is held at the same potential as the semiconductor substrate. (3) A semiconductor device having multilayer wiring according to claim 1, wherein a plurality of wiring layers are provided on an element isolation insulating film on a semiconductor substrate.