JPS62250664A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS62250664A JPS62250664A JP9418986A JP9418986A JPS62250664A JP S62250664 A JPS62250664 A JP S62250664A JP 9418986 A JP9418986 A JP 9418986A JP 9418986 A JP9418986 A JP 9418986A JP S62250664 A JPS62250664 A JP S62250664A
- Authority
- JP
- Japan
- Prior art keywords
- potential
- conductive layer
- layer
- parasitic
- parasitic fet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 239000004020 conductor Substances 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 5
- 230000003071 parasitic effect Effects 0.000 abstract description 20
- 238000009792 diffusion process Methods 0.000 abstract description 9
- 230000010354 integration Effects 0.000 abstract description 8
- 230000000694 effects Effects 0.000 abstract description 7
- 238000002955 isolation Methods 0.000 abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 6
- 230000005684 electric field Effects 0.000 abstract description 2
- 230000002542 deteriorative effect Effects 0.000 abstract 1
- 239000002245 particle Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
本発明は、第一導電型の半導体層の中に表面に露出する
二つの第二導電型の半導体領域を有し、その二つの第二
導電型の半導体領域上にまたがって絶縁膜を介して導体
層が形成される半導体集積回路に関する。The present invention has two semiconductor regions of a second conductivity type exposed to the surface in a semiconductor layer of a first conductivity type, and an insulating film is provided over the two semiconductor regions of the second conductivity type. The present invention relates to a semiconductor integrated circuit in which a conductor layer is formed.
半導体集積回路において、複数の拡散抵抗を一つのPN
接合分離された領域に配置することが知られている。第
2図に示す例においては、29分1m fil域lによ
り他の島と分離されているN″領域島) 2に二つのP
拡散抵抗3が存在している。
島2の電位は、電源ライン4を介して電源電圧まで引き
上げられており、このときP拡散抵抗3の電位は電源電
圧以下であるため、拡散抵抗3と島2との間のPN接合
は逆バイアスとなって両抵抗の間および抵抗3と分離領
域1の間の絶縁が保たれる。
ところで、ここで第3図に示すように拡散抵抗3の上を
図示しない絶縁膜を介してグランドライン5が通過する
場合を考えると、グランドライン5がゲートの役目を果
たして、抵抗3の間にPチャネルが形成される寄生FE
Tが生じてしまう危険性がある。つまり、島2を引き上
げている電・源電圧が、この寄生PチャネルFETのし
きい値電圧の絶対値より大きい場合、第4図に示すよう
にグランドライン5の下に酸化膜10を介して存在する
N−N2の表組L5がP転してしまい、その結果隣り合
う拡散層3間が導通する。そこでこのような現象を防ぐ
ため、従来は第5図に示すようにN4拡散チヤンネルス
トツパ6を設けていた。しかしながら、このようなチャ
ンネルストッパ6を設ける場合、P拡散抵抗3とチャン
ネルストッパ6の間および分I1wI域1とチャンネル
ストッパ6の間の耐圧を保つため、その距離を充分にと
る必要がある。このため、この方法は高集積化に向いて
いない。
このような寄生FET効果はバイポーラトランジスタに
おいても起こりうる。ラテラルPNP )ランジスタに
おいては、コレクタ・分離領域間で、またパーティカル
NPN l−ランジスタにおいては、ベース・分1m
81域間で寄生PチャネルFETが形成されるおそれが
ある。そこで、従来はラテラルPNP )ランジスタに
おいては、第6図に示すようにN°ベース領域7によっ
てP0エミッタ領域9を囲むP゛コレクタ領域8をさら
に囲んでコレクタ領域8と分離領域1の間のチャンネル
ストッパを構成し、パーティカルNPNトランジスタに
おいては、第7図に示すようにN3コレクタ層11によ
って内部にN0エミンタ$I域13を含むP°ベース領
域12を囲んでベース領域12と分M 61域1の間の
チャンネルストッパを構成していた。この場合において
も、高耐圧化のため膨大な面積を必要とし、高集積化の
大きな障害となっていた。
以上のことは、(111)結晶方位のシリコンウェハで
はN−濃度が数Ωam、ill化膜厚が1.5μ程度で
しきい値電圧が約−50vであるため、通常のバイポー
ラトランジスタの回路においては寄生FET効果の影響
は少ないが、(10G)結晶方位のシリコンウェハを用
いる場合、そのしきい値電圧が一10数Vまで落ち、そ
の影響は深刻である。In semiconductor integrated circuits, multiple diffused resistors are integrated into one PN.
It is known to place them in junction-separated regions. In the example shown in Figure 2, there are two P
A diffused resistor 3 is present. The potential of the island 2 is pulled up to the power supply voltage via the power supply line 4, and at this time, the potential of the P diffused resistor 3 is below the power supply voltage, so the PN junction between the diffused resistor 3 and the island 2 is reversed. A bias is maintained between the two resistors and between the resistor 3 and the isolation region 1. By the way, if we consider the case where the ground line 5 passes over the diffused resistor 3 via an insulating film (not shown) as shown in FIG. Parasitic FE where P channel is formed
There is a risk that T will occur. In other words, if the power source voltage that pulls up the island 2 is greater than the absolute value of the threshold voltage of this parasitic P-channel FET, a The existing N-N2 table set L5 is turned P, and as a result, the adjacent diffusion layers 3 are electrically connected. In order to prevent such a phenomenon, an N4 diffusion channel stopper 6 was conventionally provided as shown in FIG. However, when such a channel stopper 6 is provided, it is necessary to provide sufficient distance between the P diffused resistor 3 and the channel stopper 6 and between the I1wI region 1 and the channel stopper 6 in order to maintain the withstand voltage between them. Therefore, this method is not suitable for high integration. Such parasitic FET effects can also occur in bipolar transistors. In lateral PNP) transistors, between the collector and isolation region, and in particle NPN l-transistors, between the base and the 1 m
There is a possibility that a parasitic P-channel FET may be formed between the 81 regions. Therefore, in the conventional lateral PNP transistor, as shown in FIG. In the particle NPN transistor, which constitutes a stopper, as shown in FIG. It constituted a channel stopper between 1 and 2. In this case as well, a huge area is required to achieve high voltage resistance, which is a major obstacle to high integration. The above is because in a silicon wafer with (111) crystal orientation, the N- concentration is several Ωam, the illumination film thickness is about 1.5μ, and the threshold voltage is about -50V, so in a normal bipolar transistor circuit. The influence of the parasitic FET effect is small, but when using a silicon wafer with a (10G) crystal orientation, the threshold voltage drops to 110-odd V, and the influence is serious.
本発明は、第一導電型の半導体層の表面に露出する二つ
の第二導電型の半導体領域上に絶縁膜を介してまたがる
導体層によつて形成さる寄生FET効果を防止し、しか
もそれにより集積度を低くすることなく高耐圧化が可能
な半導体集積回路を提供することを目的とする。The present invention prevents the parasitic FET effect formed by a conductor layer spanning two second conductivity type semiconductor regions exposed on the surface of a first conductivity type semiconductor layer with an insulating film interposed therebetween. An object of the present invention is to provide a semiconductor integrated circuit that can achieve high breakdown voltage without lowering the degree of integration.
本発明は、寄生FETが形成される二つの第二導電型の
領域の中間の上に寄生FETのゲートとなる導体層の電
位と異なる電位が印加される第二の導体層を、第一の導
体層と半導体基体の間にそれぞれに絶縁して備えるもの
で、第二の導電層に印加される電位と第一導電型の半導
体層の電位との差を寄生FETのしきい値電圧以下にす
ることにより寄生FET効果が防止されるので上記の目
的を達成することができる。In the present invention, a second conductive layer, to which a potential different from the potential of the conductive layer serving as the gate of the parasitic FET is applied, is applied between the two second conductivity type regions where the parasitic FET is formed. A conductor layer and a semiconductor substrate are provided insulated between each other to reduce the difference between the potential applied to the second conductive layer and the potential of the first conductivity type semiconductor layer to below the threshold voltage of the parasitic FET. By doing so, the parasitic FET effect is prevented, so that the above object can be achieved.
以下図を引用して本発明の実施例について説明する。各
図において、第2図ないし第6図と共通の部分には同一
の符号が付されている。第1図(alは拡散抵抗を育す
る島の透視平面図、第11!1(blは(a)のA−A
線断面図である0図かられかるようにグランドライン5
とは別の層の導電層14を寄生FETのチャンネルを横
切るように設ける。この導電層14に適当な電位を印加
することにより、グランドライン5による電界を遮蔽し
チャンネルストッパの役目を果たす、これにより隣り合
うP拡散抵抗3間、あるいはP4分離領域1と拡散抵抗
3が反転層15により短絡されることはない、このため
、導電層4に印加される電位は、島2との電位差が寄生
FETのしきい値を超えないことが必要である。この例
においては、導電7114は多結晶シリコンで形成し、
島を引き上げている電位を電源ライン4からコンタクト
ホール20を介して印加している。IVの多層配線を用
いている場合は、グランドライン5とは異なる層と同時
にMで導tF114を形成してもよい、グランドライン
5との間の絶縁のために絶縁膜16を設ける。
第8図(al、(blに別の実施例を示す、YAい酸化
膜15上に多結晶シリコン7124を設はイオン注入を
行う (図a)s これにより、P拡散N3が形成され
、同時に多結晶シリコンがドープされて導体層14が生
ずる (図b)、この方法においては、多結晶シリコン
層24が拡散N3のマスクの役目を果たし、かつ適当な
電位を印加することにより、チャンネルストッパの役目
を果たす。
第9図はラテラルPNP )ランジスタにおける実施例
で、第二導体層14がP゛コレクタ領域8とP゛分離領
域lの間の表面に絶縁膜を介して形成されており、コン
タクトホール20によりN0ベース領域7に接続するこ
とによってNベース層と等しい電位が印加されてチャン
ネルストッパの役目を果たし、コレクタ領域81分離領
域1をソース・ドレインとする寄生FETの形成を防い
でいる。
第10図はパーティカルNPN )ランジスタにおける
実施例で、第二導体層14はP9ベース領域12とP゛
分1f!l ml域1の間の表面に絶縁膜を介して形成
されており、コンタクトホール20によりN0コレクタ
領域11に接続することによってNコレクタ層と等しい
電位が印加されてチャンネルストッパの役目を果たし、
ベース領域129分離領域1をソース・ドレインとする
寄生FETの形成を防いでいる。
Aj&!線あるいは多結晶シリコン層によるチャンネル
ストッパは、半導体基体と酸化膜により絶縁されている
ため、拡散領域によるチャンネルストッパと異なり、寄
生FETのソース・ドレインとなる逆導電型の領域と距
離をとる必要がなく、高集積化に最適である。Embodiments of the present invention will be described below with reference to the drawings. In each figure, parts common to those in FIGS. 2 to 6 are given the same reference numerals. Figure 1 (al is a perspective plan view of the island that grows the diffusion resistance, Figure 11!1 (bl is A-A in (a)
As shown in Figure 0, which is a line cross-sectional view, the ground line 5
A conductive layer 14, which is a separate layer, is provided across the channel of the parasitic FET. By applying an appropriate potential to this conductive layer 14, it blocks the electric field due to the ground line 5 and acts as a channel stopper, thereby inverting the relationship between the adjacent P diffused resistors 3 or between the P4 isolation region 1 and the diffused resistor 3. It is not short-circuited by the layer 15. Therefore, it is necessary that the potential applied to the conductive layer 4 has a potential difference with the island 2 that does not exceed the threshold of the parasitic FET. In this example, conductor 7114 is formed of polycrystalline silicon;
A potential that raises the island is applied from the power supply line 4 through the contact hole 20. When IV multilayer wiring is used, the conductor tF 114 may be formed in M at the same time as a layer different from the ground line 5, and an insulating film 16 is provided for insulation between the ground line 5 and the ground line 5. Another example is shown in FIG. 8(al) and (bl). Polycrystalline silicon 7124 is placed on the YA oxide film 15 and ions are implanted (FIG. 8a)s. As a result, P diffusion N3 is formed, and at the same time The polycrystalline silicon is doped to form a conductor layer 14 (FIG. b); in this method, the polycrystalline silicon layer 24 serves as a mask for the diffusion N3, and by applying a suitable potential, the channel stopper is Fig. 9 shows an embodiment of a lateral PNP transistor, in which a second conductor layer 14 is formed on the surface between the P' collector region 8 and the P' isolation region l with an insulating film interposed therebetween. By connecting to the N0 base region 7 through the hole 20, a potential equal to that of the N base layer is applied, thereby serving as a channel stopper and preventing the formation of a parasitic FET with the collector region 81 and isolation region 1 as the source and drain. FIG. 10 shows an embodiment of a particle NPN transistor, in which the second conductor layer 14 is connected to the P9 base region 12 and the P9 base region 1f! It is formed on the surface between the 1 ml regions 1 via an insulating film, and is connected to the N0 collector region 11 through a contact hole 20, so that a potential equal to that of the N collector layer is applied, and it plays the role of a channel stopper.
The base region 129 prevents the formation of a parasitic FET using the isolation region 1 as the source and drain. Aj&! A channel stopper made of a line or a polycrystalline silicon layer is insulated from the semiconductor substrate by an oxide film, so unlike a channel stopper made of a diffusion region, it is necessary to keep a distance from the regions of the opposite conductivity type that serve as the source and drain of the parasitic FET. It is ideal for high integration.
本発明によれば、半導体基体の第一導電型の層内に形成
される二つの第二導電型の領域の上にまたがる配線など
の導体層によって生ずる寄生MO3FET効果を、その
導体層と基体の中間に第二の導体層を設けて所定の電位
を印加することにより防止するもので、従来のチャンネ
ルストッパによる防止と異なり高耐圧化の障害とならず
、集積度を低下させる必要もないので、高耐圧半導体集
積回路の高集積化に極めて有効である。According to the present invention, the parasitic MO3FET effect caused by a conductor layer such as a wiring that extends over two regions of a second conductivity type formed in a layer of a first conductivity type of a semiconductor substrate can be suppressed. This is prevented by providing a second conductor layer in the middle and applying a predetermined potential. Unlike prevention using a conventional channel stopper, this does not become an obstacle to achieving high voltage resistance, and there is no need to reduce the degree of integration. It is extremely effective in increasing the degree of integration of high-voltage semiconductor integrated circuits.
第1図は本発明の一実施例を示し、talは透視平面図
、 (blは(alのA−Afi断面図、第2図、第3
図は従来の拡散抵抗部を示す透視平面図、第4図は第3
図のB−B線断面図、第5図は従来の拡散抵抗部の他の
例の透視平面図、第6図は従来のラテラルトランジスタ
部の透視平面図、第7図は従来のパーティカルトランジ
スタ部の透視平面図、第8図は本発明の別の実施例の拡
散抵抗形成工程を順次示す断面図、第9図は本発明の実
施例におけるラテラルトランジスタ部の透視平面図、第
10図は本発明の実施例におけるパーティカルトランジ
スタ部の透視平面図である。
l:分離eM 域、2:N−fig、l拡を抵抗、4:
電源ライン、5ニゲランドライン、7:N”ベース領域
、8:P0コレクタ領域、9:P0エミッタ領域、10
二酸化膜、11FN” コレクタ領域、12:P”ベー
ス領域、13:N4エミツタ領域、14:第二導電層、
16:絶縁膜、20:コンタクトホール。
第1図
第5図
第6図 第7図FIG. 1 shows an embodiment of the present invention, tal is a perspective plan view, (bl is an A-A sectional view of (al), FIGS. 2 and 3
The figure is a perspective plan view showing a conventional diffusion resistance section, and FIG.
5 is a perspective plan view of another example of a conventional diffused resistor section, FIG. 6 is a perspective plan view of a conventional lateral transistor section, and FIG. 7 is a perspective plan view of a conventional particle transistor section. 8 is a cross-sectional view sequentially showing the steps of forming a diffused resistor in another embodiment of the present invention. FIG. 9 is a perspective plan view of a lateral transistor section in an embodiment of the present invention. FIG. 2 is a perspective plan view of a particle transistor section in an embodiment of the present invention. l: separation eM area, 2: N-fig, l expansion resistor, 4:
Power supply line, 5 Nigerland line, 7: N'' base region, 8: P0 collector region, 9: P0 emitter region, 10
Dioxide film, 11FN" collector region, 12: P" base region, 13: N4 emitter region, 14: second conductive layer,
16: Insulating film, 20: Contact hole. Figure 1 Figure 5 Figure 6 Figure 7
Claims (1)
二つの第二導電型の領域を有し、該二つの領域上にまた
がって絶縁膜を介して導体層が存在するものにおいて、
前記二つの第二導電型の領域の中間の上に前記導体層の
電位と異なる電位が印加される第二の導体層が前記導体
層と半導体基体の間にそれぞれに絶縁して備えられたこ
とを特徴とする半導体集積回路。1) In a semiconductor substrate having two regions of the second conductivity type exposed to the surface in the layer of the first conductivity type, and a conductor layer existing over the two regions with an insulating film interposed therebetween. ,
A second conductor layer to which a potential different from the potential of the conductor layer is applied between the two regions of the second conductivity type is provided between the conductor layer and the semiconductor substrate insulated from each other. A semiconductor integrated circuit characterized by:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9418986A JPS62250664A (en) | 1986-04-23 | 1986-04-23 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9418986A JPS62250664A (en) | 1986-04-23 | 1986-04-23 | Semiconductor integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62250664A true JPS62250664A (en) | 1987-10-31 |
Family
ID=14103356
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9418986A Pending JPS62250664A (en) | 1986-04-23 | 1986-04-23 | Semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62250664A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02260538A (en) * | 1989-03-31 | 1990-10-23 | Fujitsu Ltd | Semiconductor device |
JPH0390459U (en) * | 1989-12-28 | 1991-09-13 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57201048A (en) * | 1981-06-03 | 1982-12-09 | Toshiba Corp | Semiconductor device |
JPS60161667A (en) * | 1984-02-01 | 1985-08-23 | Sanyo Electric Co Ltd | Lateral transistor |
-
1986
- 1986-04-23 JP JP9418986A patent/JPS62250664A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57201048A (en) * | 1981-06-03 | 1982-12-09 | Toshiba Corp | Semiconductor device |
JPS60161667A (en) * | 1984-02-01 | 1985-08-23 | Sanyo Electric Co Ltd | Lateral transistor |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02260538A (en) * | 1989-03-31 | 1990-10-23 | Fujitsu Ltd | Semiconductor device |
JPH0390459U (en) * | 1989-12-28 | 1991-09-13 |
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