JPS62250664A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To obtain a semiconductor integrated circuit, which prevents a parasitic FET effect and withstanding voltage of which can be increased without deteriorating the degree of integration, by bringing the difference of potential applied to a second conductive layer and the potential of a first conductivity type semiconductor layer to the threshold voltage or less of a parasitic FET. CONSTITUTION:A conductive layer 14 as a layer separate from a ground line 5 is formed so as to cross a channel for a parasitic FET. Proper potential is applied to the conductive layer 14, thus shielding an electric field by the ground line 5, then filling the role of a channel stopper. Consequently, adjacent P diffusion resistors 3 or a P<+> isolation region 1 and the diffusion resistors 3 are not short-circuited by inversion layers 15. As a result, potential with an island 2 need not exceed the threshold value of a parasitic FET at potential applied to the conductive layer 14. The conductive layer 14 is shaped by polycrystalline silicon, and potential pulling up the island is applied through a contact hole 20 from a power line 4. Accordingly, the trouble of hindrance against the increase of withstanding voltage is not generated, and the degree of integration need not be deteriorated.

Description

[Detailed description of the invention] [Technical field to which the invention pertains]

The present invention has two semiconductor regions of a second conductivity type exposed to the surface in a semiconductor layer of a first conductivity type, and an insulating film is provided over the two semiconductor regions of the second conductivity type. The present invention relates to a semiconductor integrated circuit in which a conductor layer is formed.

[Prior art and its problems]

In semiconductor integrated circuits, multiple diffused resistors are integrated into one PN.
It is known to place them in junction-separated regions. In the example shown in Figure 2, there are two P
A diffused resistor 3 is present. The potential of the island 2 is pulled up to the power supply voltage via the power supply line 4, and at this time, the potential of the P diffused resistor 3 is below the power supply voltage, so the PN junction between the diffused resistor 3 and the island 2 is reversed. A bias is maintained between the two resistors and between the resistor 3 and the isolation region 1. By the way, if we consider the case where the ground line 5 passes over the diffused resistor 3 via an insulating film (not shown) as shown in FIG. Parasitic FE where P channel is formed
There is a risk that T will occur. In other words, if the power source voltage that pulls up the island 2 is greater than the absolute value of the threshold voltage of this parasitic P-channel FET, a The existing N-N2 table set L5 is turned P, and as a result, the adjacent diffusion layers 3 are electrically connected. In order to prevent such a phenomenon, an N4 diffusion channel stopper 6 was conventionally provided as shown in FIG. However, when such a channel stopper 6 is provided, it is necessary to provide sufficient distance between the P diffused resistor 3 and the channel stopper 6 and between the I1wI region 1 and the channel stopper 6 in order to maintain the withstand voltage between them. Therefore, this method is not suitable for high integration. Such parasitic FET effects can also occur in bipolar transistors. In lateral PNP) transistors, between the collector and isolation region, and in particle NPN l-transistors, between the base and the 1 m
There is a possibility that a parasitic P-channel FET may be formed between the 81 regions. Therefore, in the conventional lateral PNP transistor, as shown in FIG. In the particle NPN transistor, which constitutes a stopper, as shown in FIG. It constituted a channel stopper between 1 and 2. In this case as well, a huge area is required to achieve high voltage resistance, which is a major obstacle to high integration. The above is because in a silicon wafer with (111) crystal orientation, the N- concentration is several Ωam, the illumination film thickness is about 1.5μ, and the threshold voltage is about -50V, so in a normal bipolar transistor circuit. The influence of the parasitic FET effect is small, but when using a silicon wafer with a (10G) crystal orientation, the threshold voltage drops to 110-odd V, and the influence is serious.

[Purpose of the invention]

The present invention prevents the parasitic FET effect formed by a conductor layer spanning two second conductivity type semiconductor regions exposed on the surface of a first conductivity type semiconductor layer with an insulating film interposed therebetween. An object of the present invention is to provide a semiconductor integrated circuit that can achieve high breakdown voltage without lowering the degree of integration.

[Key points of the invention]

In the present invention, a second conductive layer, to which a potential different from the potential of the conductive layer serving as the gate of the parasitic FET is applied, is applied between the two second conductivity type regions where the parasitic FET is formed. A conductor layer and a semiconductor substrate are provided insulated between each other to reduce the difference between the potential applied to the second conductive layer and the potential of the first conductivity type semiconductor layer to below the threshold voltage of the parasitic FET. By doing so, the parasitic FET effect is prevented, so that the above object can be achieved.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings. In each figure, parts common to those in FIGS. 2 to 6 are given the same reference numerals. Figure 1 (al is a perspective plan view of the island that grows the diffusion resistance, Figure 11!1 (bl is A-A in (a)
As shown in Figure 0, which is a line cross-sectional view, the ground line 5
A conductive layer 14, which is a separate layer, is provided across the channel of the parasitic FET. By applying an appropriate potential to this conductive layer 14, it blocks the electric field due to the ground line 5 and acts as a channel stopper, thereby inverting the relationship between the adjacent P diffused resistors 3 or between the P4 isolation region 1 and the diffused resistor 3. It is not short-circuited by the layer 15. Therefore, it is necessary that the potential applied to the conductive layer 4 has a potential difference with the island 2 that does not exceed the threshold of the parasitic FET. In this example, conductor 7114 is formed of polycrystalline silicon;
A potential that raises the island is applied from the power supply line 4 through the contact hole 20. When IV multilayer wiring is used, the conductor tF 114 may be formed in M at the same time as a layer different from the ground line 5, and an insulating film 16 is provided for insulation between the ground line 5 and the ground line 5. Another example is shown in FIG. 8(al) and (bl). Polycrystalline silicon 7124 is placed on the YA oxide film 15 and ions are implanted (FIG. 8a)s. As a result, P diffusion N3 is formed, and at the same time The polycrystalline silicon is doped to form a conductor layer 14 (FIG. b); in this method, the polycrystalline silicon layer 24 serves as a mask for the diffusion N3, and by applying a suitable potential, the channel stopper is Fig. 9 shows an embodiment of a lateral PNP transistor, in which a second conductor layer 14 is formed on the surface between the P' collector region 8 and the P' isolation region l with an insulating film interposed therebetween. By connecting to the N0 base region 7 through the hole 20, a potential equal to that of the N base layer is applied, thereby serving as a channel stopper and preventing the formation of a parasitic FET with the collector region 81 and isolation region 1 as the source and drain. FIG. 10 shows an embodiment of a particle NPN transistor, in which the second conductor layer 14 is connected to the P9 base region 12 and the P9 base region 1f! It is formed on the surface between the 1 ml regions 1 via an insulating film, and is connected to the N0 collector region 11 through a contact hole 20, so that a potential equal to that of the N collector layer is applied, and it plays the role of a channel stopper.
The base region 129 prevents the formation of a parasitic FET using the isolation region 1 as the source and drain. Aj&! A channel stopper made of a line or a polycrystalline silicon layer is insulated from the semiconductor substrate by an oxide film, so unlike a channel stopper made of a diffusion region, it is necessary to keep a distance from the regions of the opposite conductivity type that serve as the source and drain of the parasitic FET. It is ideal for high integration.

【Effect of the invention】

According to the present invention, the parasitic MO3FET effect caused by a conductor layer such as a wiring that extends over two regions of a second conductivity type formed in a layer of a first conductivity type of a semiconductor substrate can be suppressed. This is prevented by providing a second conductor layer in the middle and applying a predetermined potential. Unlike prevention using a conventional channel stopper, this does not become an obstacle to achieving high voltage resistance, and there is no need to reduce the degree of integration. It is extremely effective in increasing the degree of integration of high-voltage semiconductor integrated circuits.

[Brief explanation of drawings]

FIG. 1 shows an embodiment of the present invention, tal is a perspective plan view, (bl is an A-A sectional view of (al), FIGS. 2 and 3
The figure is a perspective plan view showing a conventional diffusion resistance section, and FIG.
5 is a perspective plan view of another example of a conventional diffused resistor section, FIG. 6 is a perspective plan view of a conventional lateral transistor section, and FIG. 7 is a perspective plan view of a conventional particle transistor section. 8 is a cross-sectional view sequentially showing the steps of forming a diffused resistor in another embodiment of the present invention. FIG. 9 is a perspective plan view of a lateral transistor section in an embodiment of the present invention. FIG. 2 is a perspective plan view of a particle transistor section in an embodiment of the present invention. l: separation eM area, 2: N-fig, l expansion resistor, 4:
Power supply line, 5 Nigerland line, 7: N'' base region, 8: P0 collector region, 9: P0 emitter region, 10
Dioxide film, 11FN" collector region, 12: P" base region, 13: N4 emitter region, 14: second conductive layer,
16: Insulating film, 20: Contact hole. Figure 1 Figure 5 Figure 6 Figure 7

Claims (1)

[Claims] 1) In a semiconductor substrate having two regions of the second conductivity type exposed to the surface in the layer of the first conductivity type, and a conductor layer existing over the two regions with an insulating film interposed therebetween. ,
A second conductor layer to which a potential different from the potential of the conductor layer is applied between the two regions of the second conductivity type is provided between the conductor layer and the semiconductor substrate insulated from each other. A semiconductor integrated circuit characterized by: