JPH02210849A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the parasitic capacitance of a signal line to a semiconductor substrate surface by a method wherein an electrically independent semiconductor layer in low conductivity or an insulating layer is formed and then this semiconductor layer or the insulating layer and the semiconductor substrate surface as well as two signal lines are isolated by respective insulating layers. CONSTITUTION:Diffused layer regions 13 and an insulating layer 14 are formed on the surface of a substrate 11 around a gate electrode 12 and then an electrically independent semiconductor layer 15 in low conductivity is formed on the insulating layer 14. Then, the other insulating layers 16, 16 covering the semiconductor layer 15 and the insulating layer 14 for setting up diffused layer region as well as the gate electrode 12 are laminatedly formed; signal lines 17, 18 are formed on the insulating layers 16, 16; furthermore, one end of the signal line 18 is laid between the insulating layers 16, 16 so as to be connected to the diffused region 13. Through these procedures, the electrically independent semiconductor layers 15 in low conductivity or the insulating layer 14 is laid between the insulating layers 16 for isolating signal lines so that the parasitic capacitance of the signal lines 17 to the semiconductor substrate surface 11 may notably be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device in which the parasitic capacitance of a signal line to a semiconductor substrate surface in a semiconductor integrated circuit is reduced.

[Conventional technology]

In a conventional semiconductor integrated circuit, for example, as shown in the cross-sectional view of FIG. 3, a diffusion layer region (3) is set on the substrate surface around a gate electrode (2) formed on the surface of a semiconductor substrate (1). An insulating layer (4) for signal line isolation is formed, and an insulating layer (5) for signal line isolation is formed in a laminated manner on this insulating layer (4) and on the gate electrode (2). Signal lines (G) (7) are formed on the insulating layer (5), and the ends of the signal lines (G) are interposed between the insulating layers (5) (5) to form the diffusion layer region (3). It is connected.

In a semiconductor device having such a structure, the capacitance between the signal line (6) and the substrate (1) is normally reduced by intervening an insulating layer (4) for setting a diffusion layer region and an insulating layer (5) for signal line separation. Approximately 0.15~0.2! D) About F/s+s+, and the capacitance of the gate electrode (2) is about 0.10-0, assuming that the vertical and horizontal dimensions are 40ttts X'1.5μm.
．． Furthermore, if the signal line in the circuit is taken into account, the capacitance of the signal line connecting, for example, an output transistor to an input transistor is the sum of the gate capacitance of the input transistor and the signal line capacitance.

[Problem to be solved by the invention]

Incidentally, in recent years, techniques for producing semiconductor integrated circuits have tended to become increasingly finer, and along with this, there has been a significant demand for faster circuit operation.

However, in the case of the above conventional example, no special measures are taken to reduce the parasitic capacitance of the signal line (6) provided in the semiconductor integrated circuit to the semiconductor substrate surface.
As mentioned above, the signal line (6) has a considerable parasitic capacitance with respect to the semiconductor substrate (1), and this has been the biggest factor hindering speeding up of the circuit operation.

The present invention was made to solve these conventional problems, and an object of the present invention is to significantly reduce the parasitic capacitance of a signal line with respect to a semiconductor substrate surface in a semiconductor integrated circuit.

[Means to solve the problem]

In order to achieve such an object, the present invention provides an electrically independent low conductivity layer between the semiconductor substrate surface and the signal line.
The present invention is characterized in that one conductor layer or insulating layer is formed on the I, and the conductor layer or insulating layer is separated from the conductor substrate surface and the signal line by the insulating layer, respectively.

[For production]

According to the above configuration, since an electrically independent low conductivity semiconductor layer or insulating layer is interposed between the signal line isolation insulating layers, the parasitic capacitance of the signal line with respect to the semiconductor substrate surface is significantly reduced. The propagation delay time of the signal line is shortened.

〔Example〕

Embodiments of the semiconductor device according to the present invention will be described in detail below with reference to the drawings. FIG. 1 shows the cross-sectional structure of the semiconductor integrated circuit in this example device, and shows the semiconductor substrate (11
) A diffusion layer region (13) is set on the substrate surface around the gate electrode (12) formed on the surface of (14
) on which an electrically independent low-conductivity ゛μ conductor layer (15)
an insulating layer (1G) for separating signal lines, covering the semiconductor layer (15) and the insulating layer (14) for setting the diffusion layer region, and covering the gate electrode (12). The signal lines (17) and (18) are formed on the insulating layer (IG) (IG), and the end of the signal line (18) is formed in a layered manner on the insulating layer (IG) (IG). I
G) It is connected to the diffusion layer region (13) by intervening therebetween.

The low conductivity semiconductor layer (I5) acts to reduce the parasitic capacitance of the signal line (I7) with respect to the semiconductor substrate (11) surface, and is formed at the same time as the gate electrode (I2) during fabrication. By doing so, it is possible to prevent an increase in the number of production steps. In this simultaneous formation, the gate electrode (position 2)
After the semiconductor layer (15) is formed of polysilicon, impurities for forming diffusions are implanted and impurities for forming P diffusions are implanted. In this case, the semiconductor layer (15) made of polysilicon on the insulating layer (14) for setting the diffusion layer region is not implanted with impurities, so the conductivity can be lowered, and the parasitic capacitance of the signal line (I7) can be reduced. The effect is remarkable.

Although the number of production steps increases, by using an insulator SiO2 instead of the low conductivity semiconductor layer (I5) made of polysilicon, the amount of reduction in parasitic capacitance of the signal line (I7) can be further increased. Can be done.

Further, since the diffusion layer region setting insulating layer (14) is uniformly formed and has few steps, it is possible to increase the total film thickness between the semiconductor substrate (11) and the signal line (17).

Figure 2 shows an example of the arrangement of semiconductor integrated circuits on the semiconductor substrate (II), in which (tS) is the input/output circuit formation area, and (20) is the input/output circuit formation area (1).
9) is an internal functional block arranged in the center, and (21) is a wiring area formed to surround the internal functional block (20), and a low conductivity semiconductor is placed in this wiring area (21). By applying the layer or insulating layer (15), the parasitic capacitance of the signal line to the surface of the semiconductor substrate (11) can be reduced.

〔Effect of the invention〕

As explained above, when using the two-conductor device of the present invention, an electrically independent low-conductivity semiconductor layer or insulating layer is formed between the semiconductor substrate surface and the signal line, and this Since the semiconductor layer or the insulating layer and the conductor substrate surface and the signal line are separated by the insulating layer, the parasitic capacitance of the signal line with respect to the conductor p-plate surface can be significantly reduced. Can be done. Therefore, since the propagation delay time of the signal line can be shortened, it can be widely applied to semiconductor devices having various integrated circuits that require high-speed operation, even though it has a relatively simple structure.
Practical use 1 - It has a remarkable effect.

[Brief explanation of the drawing]

FIG. 1 is a vertical cross-sectional view showing the structure of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a plan view showing an example of circuit arrangement on a semiconductor substrate, and FIG. 3 is a diagram showing the structure of a conventional semiconductor device. FIG. (11)...Semiconductor substrate, (14) (lft), -...
Insulating layer, (15)...Low conductivity semiconductor layer or insulating layer, (17)(18)...Signal line. ←Station @Kon-j Kozue Meisun Toichi 3rd

Claims (1)

[Claims] An electrically independent low conductivity semiconductor layer or insulating layer is formed between the semiconductor substrate surface and the signal line, and the semiconductor layer or insulating layer is insulated between the semiconductor substrate surface and the signal line, respectively. A semiconductor device characterized by being separated by layers.