JPH01222461A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01222461A JPH01222461A JP4903588A JP4903588A JPH01222461A JP H01222461 A JPH01222461 A JP H01222461A JP 4903588 A JP4903588 A JP 4903588A JP 4903588 A JP4903588 A JP 4903588A JP H01222461 A JPH01222461 A JP H01222461A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- wirings
- wiring
- insulating film
- implanted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 238000000034 method Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 6
- 239000001301 oxygen Substances 0.000 claims abstract description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 5
- 239000012535 impurity Substances 0.000 claims abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 15
- 229910052710 silicon Inorganic materials 0.000 claims description 15
- 239000010703 silicon Substances 0.000 claims description 15
- 238000010438 heat treatment Methods 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 4
- 239000011574 phosphorus Substances 0.000 abstract description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 3
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 3
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 3
- 230000002265 prevention Effects 0.000 abstract 2
- 230000004927 fusion Effects 0.000 abstract 1
- 229910052782 aluminium Inorganic materials 0.000 description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- -1 phosphorus ions Chemical class 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a semiconductor device.
近年、半導体チップの集積化に伴ない、多層配線構造に
おける断線、配線相互間のリーク電流等が問題になって
いる。In recent years, as semiconductor chips have become more integrated, problems such as disconnections in multilayer wiring structures and leakage current between wirings have become a problem.
第2図(a)〜(d)は従来の半導体装置の製造方法の
一例を説明するための工程順に示した半導体チップの断
面図である。FIGS. 2(a) to 2(d) are cross-sectional views of a semiconductor chip shown in order of steps for explaining an example of a conventional method of manufacturing a semiconductor device.
第2図(a)に示すように、半導体基板1上に絶縁膜2
を形成する0次に、絶縁1112上にCVD法により非
ドープシリコン層3を形成する6次に、第2図(b)に
示すように、非ドープシリコン層3にリンをイオン注入
することにより、所定の抵抗値にする。As shown in FIG. 2(a), an insulating film 2 is formed on a semiconductor substrate 1.
Next, an undoped silicon layer 3 is formed on the insulator 1112 by the CVD method.6 Next, as shown in FIG. 2(b), phosphorus is ion-implanted into the undoped silicon layer 3. , to a predetermined resistance value.
次に、第2図(c)に示すように、写真蝕刻法により、
配線6及び抵抗部となる部分を形成する。Next, as shown in Figure 2(c), by photolithography,
A portion that will become the wiring 6 and the resistance section is formed.
次に、第2図(d)に示すように、絶縁膜2゜配線6及
び抵抗部上に絶縁II7を形成し、さらにアルミニウム
の配線8を形成して、多層配線とすることにより、半導
体装置としていた。Next, as shown in FIG. 2(d), an insulation II 7 is formed on the insulation film 2, the wiring 6 and the resistor part, and an aluminum wiring 8 is further formed to form a multilayer wiring, thereby forming a semiconductor device. It was.
上述した従来の半導体装置の製造方法では、多層配線を
形成する場合、第2図(d)に示すように、絶縁層17
及び上層の配線8に段部を生じてしまう。In the conventional semiconductor device manufacturing method described above, when forming a multilayer wiring, as shown in FIG. 2(d), the insulating layer 17
Also, a stepped portion is generated in the upper layer wiring 8.
この段部の箇所では、絶縁IF!7の膜厚が薄くなり、
下層の配線6及び抵抗部と上層の配線8とのリーク電流
を発生させる要因となる。Insulated IF! The film thickness of 7 becomes thinner,
This becomes a cause of leakage current between the lower layer wiring 6 and the resistor section and the upper layer wiring 8.
又、上rtηの配線8ら段部を通過するため、その部分
での断線の可能性があるばかりでなく、それだけ配線距
離が長くなり、配線抵抗が高くなってしまう欠点があっ
た
本発明の目的は、多層配線を構成してら段部を、 生じ
ず、配線の断線、配線口(抗の減少、リーク電流の防止
が可能な半導体装置の製造方法を提供することにある。In addition, since the upper rtη wiring 8 passes through a step, there is a possibility of disconnection at that part, and the wiring distance becomes longer, which increases the wiring resistance. An object of the present invention is to provide a method for manufacturing a semiconductor device that can prevent step portions from forming multilayer wiring, reduce wiring breakage, reduce wiring resistance, and prevent leakage current.
本発明の半導体装置の製造方法は、半導体基板上に絶縁
膜を形成する工程と、前記絶縁膜上に非ドープシリコン
層を形成する工程と、前記非ドープシリコン層に選択的
に不純物を注入し配線及び抵抗部を形成する工程と、前
記配線及び抵抗部以外の非ドープシリコン層に酸素を注
入する工程と、熱処理して酸素とシリコンを結合せしめ
る工程とを含んで構成される。The method for manufacturing a semiconductor device of the present invention includes the steps of forming an insulating film on a semiconductor substrate, forming an undoped silicon layer on the insulating film, and selectively implanting impurities into the undoped silicon layer. The method includes a step of forming wiring and a resistor, a step of implanting oxygen into the undoped silicon layer other than the wiring and the resistor, and a step of bonding oxygen and silicon by heat treatment.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第1図(a)〜(e)は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面図である。FIGS. 1A to 1E are cross-sectional views of a semiconductor chip shown in order of steps for explaining an embodiment of the present invention.
第1図(a)に示すように、半導体基板1上に絶縁膜2
を形成する。次に、絶縁膜2上にCVD法により非ドー
プシリコン層3を形成する。As shown in FIG. 1(a), an insulating film 2 is formed on a semiconductor substrate 1.
form. Next, an undoped silicon layer 3 is formed on the insulating film 2 by the CVD method.
次に、第1図(b)に示すように、ホトレジストをマス
クとして、配線6及び抵抗部を形成する領域にリンをイ
オン注入する。Next, as shown in FIG. 1(b), using a photoresist as a mask, phosphorus ions are implanted into the region where the wiring 6 and the resistance portion are to be formed.
次に、第1図(c)に示すように、基板全面にアルミニ
ウム層10を形成する。Next, as shown in FIG. 1(c), an aluminum layer 10 is formed over the entire surface of the substrate.
次に、第1図(d)に示すように、リフトオフ法により
アルミニウム層10を選択的に残し、それをマスクとし
て、酸素をイオン注入する。しかる後、アルミニウム層
10を溶解除去する0次に、熱処理することにより、酸
化シリコン層11を形成し、これを絶縁層とする。Next, as shown in FIG. 1(d), the aluminum layer 10 is selectively left by a lift-off method, and using this as a mask, oxygen ions are implanted. Thereafter, a silicon oxide layer 11 is formed by performing a heat treatment to dissolve and remove the aluminum layer 10, and this is used as an insulating layer.
次に、第1図(e)に示すように、配線6及び酸化シリ
コン層11上に絶縁膜7を形成する。この時、配線6及
び酸化シリコン層11は平坦であるため、絶縁膜7は段
部を形成しない。次に、絶縁膜7上にアルミニウム配線
8を形成し、多層配線とする。Next, as shown in FIG. 1(e), an insulating film 7 is formed on the wiring 6 and the silicon oxide layer 11. At this time, since the wiring 6 and the silicon oxide layer 11 are flat, the insulating film 7 does not form a stepped portion. Next, aluminum wiring 8 is formed on the insulating film 7 to form a multilayer wiring.
本実施例で形成した半導体装置は、段部が形成されない
ので、上層に形成した絶縁膜に薄い部分が形成せず、リ
ーク電流を減少することができ、かつ、配線が最短の距
離で、しかも断線しないことが可能となる。In the semiconductor device formed in this example, since no stepped portion is formed, a thin portion is not formed in the insulating film formed as an upper layer, and leakage current can be reduced, and the wiring distance is the shortest. This makes it possible to avoid disconnection.
本実施例では、不純物としてリンを用いたが、ホウ素を
用いても同様の効果が得られる。In this example, phosphorus was used as an impurity, but the same effect can be obtained using boron.
以上説明したように、本発明は、非ドープシリコン層に
選択的に不純物を注入して配線及び抵抗部を形成し、エ
ツチングをせず、平坦なまま、その上面に絶縁膜及び上
層配線を形成して多層配線とするため、段部が形成され
ず、配線の断線、配線抵抗の減少、リーク電流の防止が
可能となる効果がある。As explained above, in the present invention, impurities are selectively implanted into an undoped silicon layer to form wiring and a resistor part, and an insulating film and upper layer wiring are formed on the top surface of the undoped silicon layer while the silicon layer remains flat without etching. Since multilayer wiring is formed, no step portions are formed, and it is possible to prevent wiring breakage, reduce wiring resistance, and prevent leakage current.
第1図(a)〜(e)は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面図、第2図(a
)〜(d)は従来の半導体装置の製造方法の一例を説明
するための工程順に示した半導体チップの断面図である
。
1・・・・・・半導体基板、2・・・・・・絶縁膜、3
・・・・・・非ドープシリコン層、4・・・・・・ホト
レジスト膜、6・・・・・・配線、7・・・・・・絶縁
膜、8・・・・・・アルミニウム配線、10・・・・・
・アルミニウム層、11・・・・・・酸化シリコン層。1(a) to 1(e) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention, and FIG. 2(a)
) to (d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an example of a conventional method for manufacturing a semiconductor device. 1... Semiconductor substrate, 2... Insulating film, 3
......Undoped silicon layer, 4... Photoresist film, 6... Wiring, 7... Insulating film, 8... Aluminum wiring, 10...
- Aluminum layer, 11...Silicon oxide layer.
Claims (1)
上に非ドープシリコン層を形成する工程と、前記非ドー
プシリコン層に選択的に不純物を注入し配線及び抵抗部
を形成する工程と、前記配線及び抵抗部以外の非ドープ
シリコン層に酸素を注入する工程と、熱処理して酸素と
シリコンを結合せしめる工程とを含むことを特徴とする
半導体装置の製造方法。a step of forming an insulating film on a semiconductor substrate, a step of forming an undoped silicon layer on the insulating film, a step of selectively implanting impurities into the undoped silicon layer to form a wiring and a resistance part, A method for manufacturing a semiconductor device, comprising the steps of: implanting oxygen into the undoped silicon layer other than the wiring and the resistor portion; and performing heat treatment to bond oxygen and silicon.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4903588A JPH01222461A (en) | 1988-03-01 | 1988-03-01 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4903588A JPH01222461A (en) | 1988-03-01 | 1988-03-01 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01222461A true JPH01222461A (en) | 1989-09-05 |
Family
ID=12819830
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4903588A Pending JPH01222461A (en) | 1988-03-01 | 1988-03-01 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01222461A (en) |
-
1988
- 1988-03-01 JP JP4903588A patent/JPH01222461A/en active Pending
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