JPS59228766A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS59228766A
JPS59228766A JP58103802A JP10380283A JPS59228766A JP S59228766 A JPS59228766 A JP S59228766A JP 58103802 A JP58103802 A JP 58103802A JP 10380283 A JP10380283 A JP 10380283A JP S59228766 A JPS59228766 A JP S59228766A
Authority
JP
Japan
Prior art keywords
diffused
semiconductor device
layers
conductivity type
under
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58103802A
Other languages
Japanese (ja)
Inventor
Toshiaki Ogata
尾形　俊昭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP58103802A priority Critical patent/JPS59228766A/en
Publication of JPS59228766A publication Critical patent/JPS59228766A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To improve the decreasing withstand voltage of a semiconductor element due to microminiaturization by forming a diffused layer region under a field oxidized film without discontinuity on the periphery of a diffused layer of high impurity density. CONSTITUTION:Stopper diffused layers 12a, 12b, 13a-13c are formed under selectively oxidized films 11a, 11d, 11g to prevent the inversion of the surface of a semiconductor. Diffused regions 11a-11c, 15a-15c are formed under the films 11b-11e in the same step as or separate step from the stopper diffused layers, contacted with the diffused layers 16a, 16b, 17a, 17b of the same conductive type high impurity density to form source and drain diffused layers. In this example, the layers 16b, 17e are surrounded by the regions 14b, 14c and 15a, 15b under the selectively oxidized films to substantially alleviate the concentration of an electric field in the drain diffused layer. When thus constructed, the withstand voltage of a semiconductor element can be improved.

Description

【発明の詳細な説明】 本発明は半導体装置、詳しくはＭＯ８Ｏ８電界効果半導
体金子する半導体装置の拡散層の構造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a structure of a diffusion layer of a semiconductor device using an MO8O8 field effect semiconductor.

半導体装置の微細化が進むにつれて、ＭＯ８電界効果半
導体素子においてはゲート膜厚の減少。As the miniaturization of semiconductor devices progresses, the gate film thickness in MO8 field effect semiconductor devices decreases.

拡散層深さの減少によって耐圧が低下して来ているが、
出力端子においては数十ボルト程度の比較的高い電圧で
の動作が要求される事が多い。上記の要求に対する解決
策の１つが第１図に平面図を第２図に断面図を示したＭ
Ｏ８電界効果半導体素子である。選択酸化膜１α、ｌｄ
、１ｇの下には半導体基板表面の反転を防止する目的で
いわゆるストッパ拡散層２α、２ｂ、３ＣＬ、３ｂ、３
Ｃ力；形成されている。上記ストツノく拡散層と同時に
もしくは別に形成された選択酸化膜ｌｂ、ｌＣ及び１ｅ
、１ｆ下の拡散領域４ａ、４ｂ、５ａ、５ｂを同じ導電
型の高不純物一度の拡散層６α、６ｂ及び７ａ、７ｂと
接続してソース及びドレイン拡散層として使用する事に
より、萬不純物饋度の拡散層のみでドレイン拡散層を形
成したＭ　ＯＳ電界効果半導体素子よフ耐圧を向上させ
る事が出来る。The withstand voltage is decreasing due to the decrease in the depth of the diffusion layer, but
The output terminal is often required to operate at a relatively high voltage of several tens of volts. One of the solutions to the above requirements is the M
It is an O8 field effect semiconductor device. Selective oxide film 1α, ld
, 1g are so-called stopper diffusion layers 2α, 2b, 3CL, 3b, 3 for the purpose of preventing the surface of the semiconductor substrate from inverting.
C force; formed. Selective oxide films lb, lc and 1e formed simultaneously with or separately from the above-mentioned diffusion layer
By connecting the diffusion regions 4a, 4b, 5a, 5b under , 1f with the high impurity diffusion layers 6α, 6b and 7a, 7b of the same conductivity type and using them as source and drain diffusion layers, the impurity concentration is It is possible to improve the breakdown voltage compared to a MOS field effect semiconductor device in which a drain diffusion layer is formed using only the diffusion layer.

しかし、上記の従来の改良されたＭＯ８電界効果半導体
素子においては耐圧の向上は高年糸ｆｉ　！Ｖａ　Ｃ度
の拡散層６α、６ｂ、７ａ、７ｂのジャンクション耐圧
がチャネル部のオフ耐圧より低くなって素子の耐圧が制
限されるためその値は拡散層が０．６μ程度の深さに形
成された素子においては３０　Ｖを越えない。However, in the above-mentioned conventional improved MO8 field effect semiconductor device, the improvement in withstand voltage is high! The junction breakdown voltage of the VaC diffusion layers 6α, 6b, 7a, and 7b is lower than the off-breakdown voltage of the channel portion, which limits the breakdown voltage of the device. The voltage does not exceed 30 V for devices with high voltage.

本発明は上記の欠点を除去して微細化により低下する半
導体素子の耐圧を向上する事を月的とする。本発明の実
施例を第３図に平面図、第４図に断面図で示す。本発明
の実施例においては高不純物濃度の拡散層の周囲に切れ
目なくフィールド酸化膜下の拡散層領域を形成する事に
よってジャンクション耐圧を向上し、素子の耐圧を向上
させるものである。選択酸化膜１１α、　１１　ｄ　、
　１１　ｇの下には半導体表面の反転を防止する目的で
いわゆるストッパ拡散層１２ａ、１２ｂ及び１３ｃ　、
１３ｂ、１３ｃが形成されて−る。上記ストッパ拡散層
と同時もしくは別工程において選択酸化膜１１ｂ、ｌｌ
Ｃ，ｌｉｄ、　１１　ｅの下に拡散領域１４α、　１４
ｂ　、　１４ｃ　、　１５α。The objective of the present invention is to eliminate the above-mentioned drawbacks and improve the withstand voltage of semiconductor elements, which decreases due to miniaturization. An embodiment of the present invention is shown in a plan view in FIG. 3 and in a sectional view in FIG. In the embodiment of the present invention, the junction breakdown voltage is improved by forming a continuous diffusion layer region under the field oxide film around the high impurity concentration diffusion layer, thereby improving the breakdown voltage of the device. Selective oxide film 11α, 11d,
Below 11g, there are so-called stopper diffusion layers 12a, 12b and 13c for the purpose of preventing the semiconductor surface from inverting.
13b and 13c are formed. The selective oxide film 11b, ll is formed at the same time as the stopper diffusion layer or in a separate process.
Diffusion region 14α, 14 under C, lid, 11 e
b, 14c, 15α.

１５ｂ、１５ｃを形成し、同一導電型の高不純物濃度の
拡散層１６　ａ　、　１６　ｂ　、　１７　ａ　、　１
７　ｂと各々接しソース及びドレイン拡散層を構成する
。図の実施例においてはドレイン拡散層１６ｂ、１７ａ
を各々選択酸化膜下の拡散領域１４ｂ、１４Ｃと］５α
、１５ｂがと９囲み、実質的にドレイン拡散層における
電界集中を緩和する事によって耐圧を向上させている。15b, 15c are formed, and diffusion layers 16a, 16b, 17a, 1 of the same conductivity type and with high impurity concentration are formed.
7b, forming source and drain diffusion layers. In the illustrated embodiment, drain diffusion layers 16b, 17a
respectively with the diffusion regions 14b and 14C under the selective oxide film ]5α
, 15b are surrounded by and 9, and the withstand voltage is improved by substantially alleviating electric field concentration in the drain diffusion layer.

ソース拡散層においても同様の構造を採っても良い。A similar structure may also be adopted in the source diffusion layer.

以上実施例にさいては相補型半導体素子の両チャネルを
高耐圧化した構造を示したが、片方のチャネルであって
も良い事は言う丑でもない。In the above embodiments, a structure is shown in which both channels of the complementary semiconductor element have a high breakdown voltage, but it goes without saying that only one channel may be used.

また抵抗として使用する拡散層においても、選択酸化膜
化の同一導電型拡散層によってとシ囲む事によって高耐
圧化が可能である。Further, even in the diffusion layer used as a resistor, it is possible to increase the breakdown voltage by surrounding it with a diffusion layer of the same conductivity type formed into a selective oxidation film.

以上述べた様に本発明の半導体装置は集積度の高い素子
と同一工程で同一チップ上に形成できる比較的耐圧の高
い素子である事から液晶グラフィック表示素子等の駆動
用半導体装置等に特に優れた効果を示す。As described above, the semiconductor device of the present invention is an element with a relatively high breakdown voltage that can be formed on the same chip in the same process as a highly integrated element, so it is particularly suitable for driving semiconductor devices such as liquid crystal graphic display elements. This shows the effect of

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の半導体装置の平面図。 第２図は従来の半導体装置の断面図。 第３図は本発明の半導体装置の平面図。 第４図は本発明の半導体装置の断面図。 １α〜１　ｇ、　１１α〜１１　ｇ・・・フィールド酸
化ｇμ２　ａ　〜ｂ　、　３　ａ　Ｎｃ　、１２α〜ｂ
、１３α〜Ｃ・・・ストッパ拡散層　４α〜ｂ、５α〜
ｂ、１４α〜Ｃ，１５α〜Ｃ・・・拡散領域 ６α〜ｂ、７ｃ〜ｂ、１６α〜ｂ、１７α〜ｂ・・・高
濃度拡散層 以　　　上 出願人　株式会社諏訪精工舎 代理人　・弁理士最　上　　務 象 −２９９FIG. 1 is a plan view of a conventional semiconductor device. FIG. 2 is a sectional view of a conventional semiconductor device. FIG. 3 is a plan view of the semiconductor device of the present invention. FIG. 4 is a sectional view of the semiconductor device of the present invention. 1α~1g, 11α~11g...Field oxidation gμ2a~b, 3aNc, 12α~b
, 13α~C... stopper diffusion layer 4α~b, 5α~
b, 14α~C, 15α~C...Diffusion region 6α~b, 7c~b, 16α~b, 17α~b...High concentration diffusion layer or higher Applicant Suwa Seikosha Co., Ltd. Agent/Patent attorney Mogami Muse-299

Claims (1)

【特許請求の範囲】 １、半導体基体に、各々主表面を有する第１及び第２の
導電型領域を有する半導体装置において、第１導電型領
域に形成された第２導電型拡散領域の少なくとも１つが
、選択酸化法によって形成されたフィールド絶縁膜下の
第２導電型拡散領域によっ−てとフ囲まれた事を特徴と
する半導体装置。 ２、前記フィールド絶縁膜下の第２導電型拡散領域は、
第２導電型領域のフィールド絶縁膜下の第２４電型不純
物層と同時に形成されたものである事を特徴とする請求
の範囲第１項記載の半導体装置。[Claims] 1. In a semiconductor device having first and second conductivity type regions each having a main surface in a semiconductor substrate, at least one of the second conductivity type diffusion regions formed in the first conductivity type region 1. A semiconductor device characterized in that the semiconductor device is surrounded by a second conductivity type diffusion region under a field insulating film formed by a selective oxidation method. 2. The second conductivity type diffusion region under the field insulating film is
2. The semiconductor device according to claim 1, wherein the semiconductor device is formed simultaneously with the 24th conductivity type impurity layer under the field insulating film in the second conductivity type region.
JP58103802A 1983-06-10 1983-06-10 Semiconductor device Pending JPS59228766A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58103802A JPS59228766A (en) 1983-06-10 1983-06-10 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58103802A JPS59228766A (en) 1983-06-10 1983-06-10 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS59228766A true JPS59228766A (en) 1984-12-22

Family

ID=14363525

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58103802A Pending JPS59228766A (en) 1983-06-10 1983-06-10 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS59228766A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0189208A2 (en) * 1985-01-25 1986-07-30 Nissan Motor Co., Ltd. Mos transistor with higher withstand voltage
US4990982A (en) * 1987-08-25 1991-02-05 Mitsubishi Denki Kabushiki Kaisha Semiconductor device of high breakdown voltage
US5043788A (en) * 1988-08-26 1991-08-27 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with functional portions having different operating voltages on one semiconductor substrate

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0189208A2 (en) * 1985-01-25 1986-07-30 Nissan Motor Co., Ltd. Mos transistor with higher withstand voltage
US4990982A (en) * 1987-08-25 1991-02-05 Mitsubishi Denki Kabushiki Kaisha Semiconductor device of high breakdown voltage
US5043788A (en) * 1988-08-26 1991-08-27 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with functional portions having different operating voltages on one semiconductor substrate

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