DE10303643B3 - Electrical connection of active semiconductor structures with the substrate, at a silicon-on-insulator semiconductor wafer, has a passage opening through the insulating layer for a metal filling covered by a layered stack - Google Patents

Electrical connection of active semiconductor structures with the substrate, at a silicon-on-insulator semiconductor wafer, has a passage opening through the insulating layer for a metal filling covered by a layered stack Download PDF

Info

Publication number
DE10303643B3
DE10303643B3 DE2003103643 DE10303643A DE10303643B3 DE 10303643 B3 DE10303643 B3 DE 10303643B3 DE 2003103643 DE2003103643 DE 2003103643 DE 10303643 A DE10303643 A DE 10303643A DE 10303643 B3 DE10303643 B3 DE 10303643B3
Authority
DE
Germany
Prior art keywords
substrate
layer
metal
metal filling
active semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE2003103643
Other languages
German (de)
Inventor
Steffen Richter
Wolfgang Göttlich
Dirk Dr. Nuernbergk
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
X Fab Semiconductor Foundries GmbH
Original Assignee
X Fab Semiconductor Foundries GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by X Fab Semiconductor Foundries GmbH filed Critical X Fab Semiconductor Foundries GmbH
Priority to DE2003103643 priority Critical patent/DE10303643B3/en
Priority to EP04706605A priority patent/EP1595285A1/en
Priority to PCT/DE2004/000146 priority patent/WO2004068574A1/en
Priority to DE112004000646T priority patent/DE112004000646D2/en
Priority to US10/543,896 priority patent/US7485926B2/en
Application granted granted Critical
Publication of DE10303643B3 publication Critical patent/DE10303643B3/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts

Abstract

Electrical connection (20) of active semiconductor structures, on or in a monocrystalline silicon layer (12) at the leading side (V) of a silicon-on-insulator (SOI) semiconductor wafer (10), with the substrate (13) passes through an insulating layer (11) to make a resistive or Schottky contact (13c) with the substrate. A stack of layers (30-32,70-72) is over the electrical connection on the insulating layer. The electrical connection is a metal filling within passage openings (19) through the insulating layer to the substrate. The stack of layers includes a pacifying layer (30,70) of silicon nitride or plasma nitride, with an opening over the metal filling, alternating with metal layers (31,32,71,72).

Description

Die Erfindung bezieht sich auf ein Verfahren zur Herstellung von elektrischen Verbindungen zwischen Bauelementstrukturen in der aktiven Halbleiterschicht von SOI(Silicon-on-Insulator)-Halbleiterscheiben und dem Halbleitersubstrat, die durch die Isolatorschicht führen, wobei von einem durch die Oxidschicht hindurchgehenden Metallkontakt mehrere voneinander getrennte Leitungen in die Schaltungsteile der aktiven oberen Halbleiterschicht laufen.The invention relates to a Method of making electrical connections between Device structures in the active semiconductor layer of SOI (silicon-on-insulator) semiconductor slices and the semiconductor substrate passing through the insulator layer, wherein from a passing through the oxide layer metal contact several separate lines in the circuit parts of the active run upper semiconductor layer.

Eine SOI-Struktur besteht aus einer dünnen Halbleiterschicht, welche sich auf einer dünnen Oxidschicht befindet. Die Oxidschicht wird üblicherweise als vergrabenes Oxid (buried oxide: BOX) erzeugt und liegt wiederum auf einer Halbleiterschicht, im allgemeinen einer Siliziumschicht, nämlich dem Siliziumsubstrat, welches gewöhnlich eine Dicke von 300 – 800μm hat. Dieses Substrat diente anfänglich nur zur Handhabung der Struktur. Die hauptsächlichen Bauelementefunktionen werden wie in gewöhnlichen CMOS-Prozessen auf homogenen Siliziumscheiben in der oberflächennahen Halbleiterschicht realisiert.An SOI structure consists of a thin semiconductor layer, which is on a thin Oxide layer is located. The oxide layer is usually buried Oxide (buried oxide: BOX) is generated and in turn lies on a semiconductor layer, generally a silicon layer, namely the silicon substrate, which usually has a thickness of 300 - 800μm. This Substrate initially served only to handle the structure. The main component functions become like in ordinary CMOS processes on homogeneous silicon wafers in the near-surface semiconductor layer realized.

Ein wesentlicher Unterschied zu den Standard-CMOS-Prozessen besteht darin, daß die Bauelemente durch Ätzungen von Gräben, die bis zur Isolationsschicht reichen, dielektrisch voneinander getrennt sind. Hierdurch wird die gegenseitige elektrische Beeinflussung der Bauelemente stark verringert. Diese dielektrische Isolation macht die SOI-Technologie auch für Hochvoltanwendungen geeignet.An essential difference to the Standard CMOS processes consist of etching the components through etching of trenches, which extend to the insulating layer, dielectrically from each other are separated. As a result, the mutual electrical influence the components greatly reduced. This dielectric isolation makes the SOI technology synonymous for High voltage applications suitable.

Einerseits bringt es Vorteile mit sich, wenn bestimmte Bauelemente nicht über das Substrat miteinander gekoppelt sind. Es entfallen dadurch bestimmte unerwünschte Substrateffekte, wie z.B. Latch-Up, signifikante Sperrströme bei erhöhten Temperaturen, erhöhte parasitäre Kapazitäten an den Source/Bulk- bzw. Drain/Bulk-pn-Übergängen. Andererseits bringt es Vorteile mit sich, wenn eine Substratverbindung besteht, z.B. auch um bestimmte im Substrat erzeugte Strukturen mit in die Schaltung einschließen zu können. Auf diese Weise sind auch Bauelemente anderer, nicht der SOI-Technologie entsprechender Verfahrensweisen integrierbar.On the one hand, it brings advantages itself when certain components do not cross the substrate with each other are coupled. It eliminates certain unwanted substrate effects, such as. Latch-up, significant reverse currents at elevated temperatures, increased parasitic capacitances at the Source / bulk / drain / bulk pn junctions. on the other hand it brings advantages if there is a substrate connection, e.g. also to certain generated in the substrate structures in the Include circuit to be able to. In this way, components of other, not the SOI technology are more appropriate Procedures integrable.

Einfache elektrische Verbindungen zwischen der aktiven Halbleiterscheibe und dem Hableitersubstrat bei SOI-Scheiben, die durch die vergrabene Oxidschicht hindurchgehen, sind bekannt. z.B. aus den Patentschriften US 61 53 912 und WO 01/99 180 A2. Bei letzterer befindet sich am Grund des Kontaktlochs, welches auf dem Substrat endet, eine dünne Oxidschicht zur Einstellung des elektrischen Widerstandes. Geläufig sind auch zur Oberseite der aktiven Schicht geführte elektrische Verbindungen, die im Substrat definiert erzeugte Dotierungsgebiete anschließen, wie das z.B. in den Schriften US 53 14 841 , US 63 00 666 B1 , WO 02/07 3667, GB 23 46 260 A offengelegt ist.Simple electrical connections between the active semiconductor wafer and the semiconductor substrate in SOI wafers passing through the buried oxide layer are known. eg from the patents US 61 53 912 and WO 01/99 180 A2. In the latter, at the bottom of the contact hole, which terminates on the substrate, there is a thin oxide layer for adjusting the electrical resistance. Also common are electrical connections conducted to the top of the active layer, which connect doping regions generated in the substrate in a defined manner, as for example in the publications US 53 14 841 . US 63 00 666 B1 , WO 02/07 3667, GB 23 46 260 A is disclosed.

Wenn es nun so ist, daß es für bestimmte gegeneinander elektrisch isolierte Gebiete der aktiven Halbeiterschicht vorteilhaft ist, mit dem Substrat verbunden zu werden, für andere jedoch wieder nachteilig, was insbesondere bei der Integration von höhersperrenden Bauelementen mit peripheren Schaltkreisen der Fall ist, dann ist es vorteilhaft, mehrere voneinander isolierte Metallbahnen mit einem Durchbruch durch die Oxidschicht zum Substrat, bzw. zu bestimmten spezifisch dotierten Gebieten im Substrat zu führen.If it is true that it is for certain against each other electrically isolated areas of the active semiconductor layer is advantageous to be connected to the substrate, for others However, again disadvantageous, which is particularly in the integration of higher blocking Components with peripheral circuits is the case, then It is advantageous to have several mutually insulated metal tracks with a Breakthrough through the oxide layer to the substrate, or to certain specifically doped regions in the substrate to lead.

Aufgabe der Erfindung ist es, eine Lösung zur Führung einer Mehrzahl von gegeneinander isolierten elektrischen Verbindungen anzugeben, die durch einen Kontaktdurchbruch durch die Oxidschicht vom Substrat zur Oberseite der aktiven Schicht einer SOI-Scheibe gehen.The object of the invention is to provide a Solution to guide a plurality of mutually insulated electrical connections indicate that by a contact breakthrough by the oxide layer from the substrate to the top of the active layer of an SOI disk walk.

Zweck der Erfindung ist es, die Technologie der Herstellung von Schaltkreisen, insbesondere unter Integration von höhersperrenden Bauelementen basierend auf einer SOI-Halbleiterscheiben-Technologie zu verbessern und die Ingrationsmöglichkeiten zu erweitern.The purpose of the invention is the technology of Production of circuits, in particular with integration of higher blocking Components based on SOI wafer technology to improve and expand the Ingrationsmöglichkeiten.

Die erfindungsgemäße Lösung ist im kennzeichnenden Teil des Anspruchs 1 dargestellt. Weitere Ausgestaltungen der Erfindung sind in den Nebenansprüchen und Unteransprüchen enthalten.The solution according to the invention is in the characterizing Part of claim 1 shown. Further embodiments of the invention are in the secondary claims and subclaims contain.

Zur näheren Erläuterung der Erfindung dient Fig. 1, sie zeigt schematisch die Kontaktierung des Substrats über einen Kontaktstapel. Die Durchführung stellt den einfachsten Fall eine Mehrfachverbindung mit dem Substrat dar. Unterschiedliche Bauelementegruppen auf der Oberseite können separat mit dem Substrat verbunden werden. Es liegt im Rahmen der Erfindung, daß gegeneinander isolierte elektrische Mehrfachverbindungen, die durch einen Kontaktdurchbruch in der Oxidschicht geführt werden, auch zum Anschluß unterschiedlicher Dotierungsgebiete, bis hin zu kompletten Bauelementen und Schaltungen im Substrat angewendet werden können.For a more detailed explanation of the invention is used Fig. 1 , It shows schematically the contacting of the substrate via a contact stack. The implementation is the simplest case, a multiple connection with the substrate. Different groups of devices on the top can be connected separately to the substrate. It is within the scope of the invention that mutually insulated electrical multiple connections, which are guided by a contact breakthrough in the oxide layer, also for connection of different doping regions, can be applied to complete components and circuits in the substrate.

An den Schnittstellen zwischen dem Metall der Durchführung durch die Oxidschicht und im einfachsten Fall dem Substrat, besteht die Möglichkeit einen bestimmten ohmschen Kontakt oder einen Schottky-Kontakt auszubilden.At the interfaces between the Metal of execution through the oxide layer and in the simplest case the substrate exists the possibility of one certain ohmic contact or a Schottky contact form.

Claims (5)

Verfahren zur Herstellung elektrischer Substratkontakte von Silicon-on-Insulator (SOI)-Halbleiterscheiben mit einem einkristallinen Substrat, einer vergrabenen Oxidschicht und einer aktiven Halbleiterschicht, in deren aktiver Halbleiterschicht oberhalb der vergrabenen Oxidschicht mehrere durch eine Isolatorschicht gegeneinander isolierte Gebiete mit Bauelementen vorgesehen sind, bei denen in die Isolatorschicht in von der aktiven Halbleiterschicht freien Bereichen Durchbrechungen eingebracht sind, welche bis zum einkristallinen Substrat reichen, die mit einem Metall gefüllt werden, wodurch eine Metallfüllung entsteht, und auf der Isolatorschicht eine Passivierungsschicht mit einer Öffnung über dem Bereich der Metallfüllung erzeugt wird, und darüber eine die Metallfüllung überdeckende Metallisierungsschicht gelegt wird, und damit ein elektrischer Kontakt vom einkristallinen Substrat zu den Bauelementen in der aktiven Halbleiterschicht hergestellt wird, dadurch gekennzeichnet, dass mehrere Schichtenfolgen als Stapel aufgebracht werden, derart, dass zuerst eine Passivierungsschicht mit einer Öffnung über dem Bereich der Metallfüllung erzeugt wird, darüber eine die Metallfüllung überdeckende Metallisierungsschicht gelegt wird, wodurch die entsprechende Stelle des Substrats mit mehreren unterschiedlichen Schaltungspunkten der in der aktiven Halbleiterschicht liegenden Bauelemente elektrisch verbunden wird.Method of making electrical substrate contacts of silicon-on-insulator (SOI) semiconductor disks with a monocrystalline substrate, a buried oxide layer and an active semiconductor layer, in whose active semiconductor layer above the buried oxide layer a plurality of insulated by an insulator layer regions are provided with components in which in the insulator layer in the free areas of the active semiconductor layer openings are introduced which extend to the monocrystalline substrate, which are filled with a metal, whereby a metal filling is formed, and on the insulator layer, a passivation layer is formed with an opening over the region of the metal filling, and above a metal filling overlapping metallization layer is laid, and thus an electrical Contact is made of monocrystalline substrate to the devices in the active semiconductor layer, characterized in that several layer sequences are applied as stacks, such that first a passivation layer is formed with an opening over the region of the metal filling, a metallization layer covering the metal filling is laid over it, whereby the corresponding point of the substrate is electrically connected to a plurality of different circuit points of the components lying in the active semiconductor layer. Verfahren nach Anspruch 1, dadurch gekennzeichnet, dass die verschiedenen Passivierungs- und Metallschichten jeweils als Bestandteil der technologischen Schrittfolge bei der Herstellung der Metallisierungsebenen einer integrierten Schaltung mit erzeugt werden.Method according to claim 1, characterized in that that the different passivation and metal layers respectively as part of the technological step sequence in the production the metallization of an integrated circuit generated become. Verfahren nach Anspruch 1, dadurch gekennzeichnet, dass die Passivierungsschicht eine Siliziumnitridschicht ist.Method according to claim 1, characterized in that the passivation layer is a silicon nitride layer. Verfahren nach Anspruch 1, dadurch gekennzeichnet, dass die Bedingungen an der Grenze Metall/Substrat so eingestellt werden, dass sich ein ohmscher Kontakt zum Substrat ausbildet. Method according to claim 1, characterized in that that set the conditions at the metal / substrate boundary so be that forms an ohmic contact to the substrate. Verfahren nach Anspruch 1, dadurch gekennzeichnet, dass die Bedingungen an der Grenze Metall/Substrat so eingestellt werden, dass sich ein Schottky-Kontakt zum Substrat ausbildet.Method according to claim 1, characterized in that that set the conditions at the metal / substrate boundary so be that forms a Schottky contact to the substrate.
DE2003103643 2003-01-30 2003-01-30 Electrical connection of active semiconductor structures with the substrate, at a silicon-on-insulator semiconductor wafer, has a passage opening through the insulating layer for a metal filling covered by a layered stack Expired - Lifetime DE10303643B3 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
DE2003103643 DE10303643B3 (en) 2003-01-30 2003-01-30 Electrical connection of active semiconductor structures with the substrate, at a silicon-on-insulator semiconductor wafer, has a passage opening through the insulating layer for a metal filling covered by a layered stack
EP04706605A EP1595285A1 (en) 2003-01-30 2004-01-30 Soi contact structure(s) and corresponding production method
PCT/DE2004/000146 WO2004068574A1 (en) 2003-01-30 2004-01-30 Soi contact structure(s) and corresponding production method
DE112004000646T DE112004000646D2 (en) 2003-01-30 2004-01-30 SOI contact structure (s) and related manufacturing process
US10/543,896 US7485926B2 (en) 2003-01-30 2004-01-30 SOI contact structures

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2003103643 DE10303643B3 (en) 2003-01-30 2003-01-30 Electrical connection of active semiconductor structures with the substrate, at a silicon-on-insulator semiconductor wafer, has a passage opening through the insulating layer for a metal filling covered by a layered stack

Publications (1)

Publication Number Publication Date
DE10303643B3 true DE10303643B3 (en) 2004-09-09

Family

ID=32841585

Family Applications (2)

Application Number Title Priority Date Filing Date
DE2003103643 Expired - Lifetime DE10303643B3 (en) 2003-01-30 2003-01-30 Electrical connection of active semiconductor structures with the substrate, at a silicon-on-insulator semiconductor wafer, has a passage opening through the insulating layer for a metal filling covered by a layered stack
DE112004000646T Withdrawn - After Issue DE112004000646D2 (en) 2003-01-30 2004-01-30 SOI contact structure (s) and related manufacturing process

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE112004000646T Withdrawn - After Issue DE112004000646D2 (en) 2003-01-30 2004-01-30 SOI contact structure (s) and related manufacturing process

Country Status (1)

Country Link
DE (2) DE10303643B3 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005046624B3 (en) * 2005-09-29 2007-03-22 Atmel Germany Gmbh Production of semiconductor arrangement with formation of conductive substrate, structural element region (SER) layer for insulating SER from substrate useful in semiconductor technology, e.g. in production of DMOS-field effect transistors
DE102008034789B4 (en) * 2007-07-25 2010-02-04 Infineon Technologies Ag A method of manufacturing a semiconductor device, a method of manufacturing an SOI device, semiconductor device, and SOI device

Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5314841A (en) * 1993-04-30 1994-05-24 International Business Machines Corporation Method of forming a frontside contact to the silicon substrate of a SOI wafer
DE4314907C1 (en) * 1993-05-05 1994-08-25 Siemens Ag Method for producing semiconductor components making electrically conducting contact with one another vertically
DE4400985C1 (en) * 1994-01-14 1995-05-11 Siemens Ag Method for producing a three-dimensional circuit arrangement
DE4433846C2 (en) * 1994-09-22 1999-06-02 Fraunhofer Ges Forschung Method of making a vertical integrated circuit structure
DE19904571C1 (en) * 1999-02-04 2000-04-20 Siemens Ag Three-dimensional IC, e.g. a DRAM cell array, is produced by electron beam passage through a substrate to locate an alignment structure in a bonded second substrate for mask alignment
GB2346260A (en) * 1999-01-28 2000-08-02 Ibm Forming trench contacts to substrates in SOI devices
DE4229628C2 (en) * 1991-09-10 2000-08-17 Mitsubishi Electric Corp Semiconductor device with a stacked structure and method for producing such a device
US6153912A (en) * 1999-10-25 2000-11-28 Advanced Micro Devices, Inc. SOI with conductive metal substrate used as VSS connection
US6188122B1 (en) * 1999-01-14 2001-02-13 International Business Machines Corporation Buried capacitor for silicon-on-insulator structure
DE10047963A1 (en) * 1999-09-28 2001-03-29 Sony Corp Making multilayer thin film component, assembles component units, each carrying component layers on supportive substrates
US6300666B1 (en) * 1998-09-30 2001-10-09 Honeywell Inc. Method for forming a frontside contact to the silicon substrate of a SOI wafer in the presence of planarized contact dielectrics
WO2001099180A2 (en) * 2000-06-16 2001-12-27 Advanced Micro Devices, Inc. Novel frontside contact to substrate of soi device
US6429477B1 (en) * 2000-10-31 2002-08-06 International Business Machines Corporation Shared body and diffusion contact structure and method for fabricating same
WO2002073667A2 (en) * 2001-03-14 2002-09-19 Honeywell International Inc. Formation of a frontside contact on silicon-on-insulator substrate

Patent Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4229628C2 (en) * 1991-09-10 2000-08-17 Mitsubishi Electric Corp Semiconductor device with a stacked structure and method for producing such a device
US5314841A (en) * 1993-04-30 1994-05-24 International Business Machines Corporation Method of forming a frontside contact to the silicon substrate of a SOI wafer
DE4314907C1 (en) * 1993-05-05 1994-08-25 Siemens Ag Method for producing semiconductor components making electrically conducting contact with one another vertically
DE4400985C1 (en) * 1994-01-14 1995-05-11 Siemens Ag Method for producing a three-dimensional circuit arrangement
DE4433846C2 (en) * 1994-09-22 1999-06-02 Fraunhofer Ges Forschung Method of making a vertical integrated circuit structure
US6300666B1 (en) * 1998-09-30 2001-10-09 Honeywell Inc. Method for forming a frontside contact to the silicon substrate of a SOI wafer in the presence of planarized contact dielectrics
US6188122B1 (en) * 1999-01-14 2001-02-13 International Business Machines Corporation Buried capacitor for silicon-on-insulator structure
GB2346260A (en) * 1999-01-28 2000-08-02 Ibm Forming trench contacts to substrates in SOI devices
DE19904571C1 (en) * 1999-02-04 2000-04-20 Siemens Ag Three-dimensional IC, e.g. a DRAM cell array, is produced by electron beam passage through a substrate to locate an alignment structure in a bonded second substrate for mask alignment
DE10047963A1 (en) * 1999-09-28 2001-03-29 Sony Corp Making multilayer thin film component, assembles component units, each carrying component layers on supportive substrates
US6153912A (en) * 1999-10-25 2000-11-28 Advanced Micro Devices, Inc. SOI with conductive metal substrate used as VSS connection
WO2001099180A2 (en) * 2000-06-16 2001-12-27 Advanced Micro Devices, Inc. Novel frontside contact to substrate of soi device
US6429477B1 (en) * 2000-10-31 2002-08-06 International Business Machines Corporation Shared body and diffusion contact structure and method for fabricating same
WO2002073667A2 (en) * 2001-03-14 2002-09-19 Honeywell International Inc. Formation of a frontside contact on silicon-on-insulator substrate

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005046624B3 (en) * 2005-09-29 2007-03-22 Atmel Germany Gmbh Production of semiconductor arrangement with formation of conductive substrate, structural element region (SER) layer for insulating SER from substrate useful in semiconductor technology, e.g. in production of DMOS-field effect transistors
DE102008034789B4 (en) * 2007-07-25 2010-02-04 Infineon Technologies Ag A method of manufacturing a semiconductor device, a method of manufacturing an SOI device, semiconductor device, and SOI device
US7982281B2 (en) 2007-07-25 2011-07-19 Infineon Technologies Ag Method of manufacturing a semiconductor device, method of manufacturing a SOI device, semiconductor device, and SOI device

Also Published As

Publication number Publication date
DE112004000646D2 (en) 2006-02-02

Similar Documents

Publication Publication Date Title
DE112019003640B4 (en) Thermal Extraction of Single Layer Transfer Integrated Circuits
US8212311B2 (en) Semiconductor device having increased gate length implemented by surround gate transistor arrangements
DE102011056157B4 (en) Method for producing a semiconductor device and semiconductor devices with isolated semiconductor mesas
KR101789063B1 (en) Semiconductor structure having column iii-v isolation regions
CN101556956B (en) Discrete power MOSFET integrated with sense fet
KR101247696B1 (en) High voltage resistor
US11031327B2 (en) Through vias and methods of formation thereof
CN103681673B (en) Semiconductor devices and method, semi-conductor device manufacturing method
EP1770786A1 (en) Semiconductor device and method of manufacturing a semiconductor device
DE1514818B2 (en)
US9111849B2 (en) High voltage resistor with biased-well
DE19811604B4 (en) Semiconductor device
DE19857059A1 (en) Silicon on insulator component
DE102011056937A1 (en) The housing
DE102013108614A1 (en) Semiconductor device and method for manufacturing the same
DE102015106185B4 (en) Semiconductor structure and method for processing a carrier
DE10300577B4 (en) Semiconductor device with vertical power device comprising a separation trench and method for its preparation
DE4314906A1 (en) Semiconductor component with power connections for high integration density
DE102014211904B4 (en) semiconductor device
DE2432544A1 (en) SEMICONDUCTOR COMPONENT WITH A DIELECTRIC SUPPORT AND THE PROCESS FOR ITS PRODUCTION
DE10303643B3 (en) Electrical connection of active semiconductor structures with the substrate, at a silicon-on-insulator semiconductor wafer, has a passage opening through the insulating layer for a metal filling covered by a layered stack
CN102468336A (en) Semiconductor device
DE102006038874A1 (en) Semiconductor device, has trench with side wall-isolation extending from main surface deeply into semiconductor substrate and comprising conductive material extending from main surface to substrate layer
DE10343132B4 (en) Isolated MOS transistors with extended drain region for increased voltages
WO2004068574A1 (en) Soi contact structure(s) and corresponding production method

Legal Events

Date Code Title Description
8100 Publication of patent without earlier publication of application
8364 No opposition during term of opposition
R071 Expiry of right