DE10303643B3 - Electrical connection of active semiconductor structures with the substrate, at a silicon-on-insulator semiconductor wafer, has a passage opening through the insulating layer for a metal filling covered by a layered stack - Google Patents

Electrical connection of active semiconductor structures with the substrate, at a silicon-on-insulator semiconductor wafer, has a passage opening through the insulating layer for a metal filling covered by a layered stack

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Publication number
DE10303643B3
DE10303643B3 DE2003103643 DE10303643A DE10303643B3 DE 10303643 B3 DE10303643 B3 DE 10303643B3 DE 2003103643 DE2003103643 DE 2003103643 DE 10303643 A DE10303643 A DE 10303643A DE 10303643 B3 DE10303643 B3 DE 10303643B3
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Prior art keywords
substrate
layer
metal
formed
metal filling
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Application number
DE2003103643
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German (de)
Inventor
Wolfgang Göttlich
Dirk Dr. Nuernbergk
Steffen Richter
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
X-Fab Semiconductor Foundries AG
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X-Fab Semiconductor Foundries AG
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743Making of internal connections, substrate contacts

Abstract

Electrical connection (20) of active semiconductor structures, on or in a monocrystalline silicon layer (12) at the leading side (V) of a silicon-on-insulator (SOI) semiconductor wafer (10), with the substrate (13) passes through an insulating layer (11) to make a resistive or Schottky contact (13c) with the substrate. A stack of layers (30-32,70-72) is over the electrical connection on the insulating layer. The electrical connection is a metal filling within passage openings (19) through the insulating layer to the substrate. The stack of layers includes a pacifying layer (30,70) of silicon nitride or plasma nitride, with an opening over the metal filling, alternating with metal layers (31,32,71,72).

Description

  • Die Erfindung bezieht sich auf ein Verfahren zur Herstellung von elektrischen Verbindungen zwischen Bauelementstrukturen in der aktiven Halbleiterschicht von SOI(Silicon-on-Insulator)-Halbleiterscheiben und dem Halbleitersubstrat, die durch die Isolatorschicht führen, wobei von einem durch die Oxidschicht hindurchgehenden Metallkontakt mehrere voneinander getrennte Leitungen in die Schaltungsteile der aktiven oberen Halbleiterschicht laufen. The invention relates to a method of making electrical connections between device structures in the active semiconductor layer of SOI (Silicon-on-Insulator) -Halbleiterscheiben and the semiconductor substrate, which pass through the insulator layer, wherein from a passing through the oxide layer metal contact several separate lines running in the circuit portions of the active upper semiconductor layer.
  • Eine SOI-Struktur besteht aus einer dünnen Halbleiterschicht, welche sich auf einer dünnen Oxidschicht befindet. An SOI structure consisting of a thin semiconductor layer which is located on a thin oxide layer. Die Oxidschicht wird üblicherweise als vergrabenes Oxid (buried oxide: BOX) erzeugt und liegt wiederum auf einer Halbleiterschicht, im allgemeinen einer Siliziumschicht, nämlich dem Siliziumsubstrat, welches gewöhnlich eine Dicke von 300 – 800μm hat. The oxide layer is commonly referred to as buried oxide (buried oxide BOX) is generated and in turn lies on a semiconductor layer, generally a silicon layer, namely the silicon substrate, which is usually a thickness of 300 - has 800 .mu.m. Dieses Substrat diente anfänglich nur zur Handhabung der Struktur. This substrate was used initially only to the handling of the structure. Die hauptsächlichen Bauelementefunktionen werden wie in gewöhnlichen CMOS-Prozessen auf homogenen Siliziumscheiben in der oberflächennahen Halbleiterschicht realisiert. The main components functions are implemented as in conventional CMOS processes on homogenous silicon wafers in the near-surface semiconductor layer.
  • Ein wesentlicher Unterschied zu den Standard-CMOS-Prozessen besteht darin, daß die Bauelemente durch Ätzungen von Gräben, die bis zur Isolationsschicht reichen, dielektrisch voneinander getrennt sind. An essential difference to the standard CMOS processes is that the components are dielectrically isolated from each other by etching trenches which extend up to the insulating layer. Hierdurch wird die gegenseitige elektrische Beeinflussung der Bauelemente stark verringert. In this way, the mutual electrical interaction of the components is greatly reduced. Diese dielektrische Isolation macht die SOI-Technologie auch für Hochvoltanwendungen geeignet. This dielectric isolation makes the SOI technology suitable for high-voltage applications.
  • Einerseits bringt es Vorteile mit sich, wenn bestimmte Bauelemente nicht über das Substrat miteinander gekoppelt sind. On the one hand it provides advantages, when certain components are not coupled to each other via the substrate. Es entfallen dadurch bestimmte unerwünschte Substrateffekte, wie zB Latch-Up, signifikante Sperrströme bei erhöhten Temperaturen, erhöhte parasitäre Kapazitäten an den Source/Bulk- bzw. Drain/Bulk-pn-Übergängen. It thus eliminating the substrate certain undesirable effects such as latch-up, significant reverse currents at elevated temperatures, increased parasitic capacity at the source / bulk or drain / bulk pn junctions. Andererseits bringt es Vorteile mit sich, wenn eine Substratverbindung besteht, zB auch um bestimmte im Substrat erzeugte Strukturen mit in die Schaltung einschließen zu können. On the other hand it provides advantages if a substrate compound is, for example, to include in the circuit also certain generated in the substrate structures. Auf diese Weise sind auch Bauelemente anderer, nicht der SOI-Technologie entsprechender Verfahrensweisen integrierbar. In this way, components of other non-SOI technology appropriate procedures are integrated.
  • Einfache elektrische Verbindungen zwischen der aktiven Halbleiterscheibe und dem Hableitersubstrat bei SOI-Scheiben, die durch die vergrabene Oxidschicht hindurchgehen, sind bekannt. Simple electrical connections between the active wafer and the Hableitersubstrat with SOI wafers, which pass through the buried oxide layer are known. zB aus den Patentschriften for example, from patents US 61 53 912 US 61 53 912 und WO 01/99 180 A2. and WO 01/99 180 A2. Bei letzterer befindet sich am Grund des Kontaktlochs, welches auf dem Substrat endet, eine dünne Oxidschicht zur Einstellung des elektrischen Widerstandes. In the latter case, a thin oxide layer to adjust the electrical resistance located at the bottom of the contact hole, which terminates on the substrate. Geläufig sind auch zur Oberseite der aktiven Schicht geführte elektrische Verbindungen, die im Substrat definiert erzeugte Dotierungsgebiete anschließen, wie das zB in den Schriften Commonly are guided to the top surface of the active layer electrical connections in the substrate defined doping regions generated connect, as the example, in documents US 53 14 841 US 53 14 841 , . US 63 00 666 B1 US 63 00 666 B1 , WO 02/07 3667, WHERE 02/07 3667, GB 23 46 260 A GB 23 46 260 A offengelegt ist. is disclosed.
  • Wenn es nun so ist, daß es für bestimmte gegeneinander elektrisch isolierte Gebiete der aktiven Halbeiterschicht vorteilhaft ist, mit dem Substrat verbunden zu werden, für andere jedoch wieder nachteilig, was insbesondere bei der Integration von höhersperrenden Bauelementen mit peripheren Schaltkreisen der Fall ist, dann ist es vorteilhaft, mehrere voneinander isolierte Metallbahnen mit einem Durchbruch durch die Oxidschicht zum Substrat, bzw. zu bestimmten spezifisch dotierten Gebieten im Substrat zu führen. If it is now so that it is for certain mutually electrically isolated regions of the active semiconductor layer advantageous to be connected to the substrate, but again disadvantageous for other thing with peripheral circuits is particularly in the integration of higher blocking components of the case, then to lead it advantageously a plurality of mutually isolated metal traces with an opening through the oxide layer to the substrate, or to certain specific doped regions in the substrate.
  • Aufgabe der Erfindung ist es, eine Lösung zur Führung einer Mehrzahl von gegeneinander isolierten elektrischen Verbindungen anzugeben, die durch einen Kontaktdurchbruch durch die Oxidschicht vom Substrat zur Oberseite der aktiven Schicht einer SOI-Scheibe gehen. The object of the invention is to provide a solution for guiding a plurality of mutually isolated electrical connections that pass through a contact breakdown through the oxide layer from the substrate to the top surface of the active layer of an SOI wafer.
  • Zweck der Erfindung ist es, die Technologie der Herstellung von Schaltkreisen, insbesondere unter Integration von höhersperrenden Bauelementen basierend auf einer SOI-Halbleiterscheiben-Technologie zu verbessern und die Ingrationsmöglichkeiten zu erweitern. Purpose of the invention is to improve the technology of production of circuits, in particular integration of higher-locking devices based on an SOI wafer technology and to expand the Ingrationsmöglichkeiten.
  • Die erfindungsgemäße Lösung ist im kennzeichnenden Teil des Anspruchs 1 dargestellt. The inventive solution is presented in the characterizing part of claim 1. Weitere Ausgestaltungen der Erfindung sind in den Nebenansprüchen und Unteransprüchen enthalten. Further embodiments of the invention are contained in the dependent claims and subclaims.
  • Zur näheren Erläuterung der Erfindung dient serves to further illustrate the invention Fig. 1 Fig. 1 , sie zeigt schematisch die Kontaktierung des Substrats über einen Kontaktstapel. , It schematically shows the contact of the substrate via a contact stack. Die Durchführung stellt den einfachsten Fall eine Mehrfachverbindung mit dem Substrat dar. Unterschiedliche Bauelementegruppen auf der Oberseite können separat mit dem Substrat verbunden werden. The implementation is the simplest case, is a multiple connection with the substrate. Different component groups on the upper side can be separately connected to the substrate. Es liegt im Rahmen der Erfindung, daß gegeneinander isolierte elektrische Mehrfachverbindungen, die durch einen Kontaktdurchbruch in der Oxidschicht geführt werden, auch zum Anschluß unterschiedlicher Dotierungsgebiete, bis hin zu kompletten Bauelementen und Schaltungen im Substrat angewendet werden können. It is within the scope of the invention that mutually insulated multiple electrical connections, which are passed through a contact aperture in the oxide layer, can also be used for connection of different doping regions, up to complete devices and circuits in the substrate.
  • An den Schnittstellen zwischen dem Metall der Durchführung durch die Oxidschicht und im einfachsten Fall dem Substrat, besteht die Möglichkeit einen bestimmten ohmschen Kontakt oder einen Schottky-Kontakt auszubilden. At the interfaces between the metal of carrying through the oxide layer and the substrate in the simplest case, there is the possibility of a certain ohmic contact or form a Schottky contact.

Claims (5)

  1. Verfahren zur Herstellung elektrischer Substratkontakte von Silicon-on-Insulator (SOI)-Halbleiterscheiben mit einem einkristallinen Substrat, einer vergrabenen Oxidschicht und einer aktiven Halbleiterschicht, in deren aktiver Halbleiterschicht oberhalb der vergrabenen Oxidschicht mehrere durch eine Isolatorschicht gegeneinander isolierte Gebiete mit Bauelementen vorgesehen sind, bei denen in die Isolatorschicht in von der aktiven Halbleiterschicht freien Bereichen Durchbrechungen eingebracht sind, welche bis zum einkristallinen Substrat reichen, die mit einem Metall gefüllt werden, wodurch eine Metallfüllung entsteht, und auf der Isolatorschicht eine Passivierungsschicht mit einer Öffnung über dem Bereich der Metallfüllung erzeugt wird, und darüber eine die Metallfüllung überdeckende Metallisierungsschicht gelegt wird, und damit ein elektrischer Kontakt vom einkristallinen Substrat zu den Bauelementen in der aktiven Halbleiterschicht hergestellt wird, dadurch gekennzeichnet , d A process for the production of electrical substrate contacts of Silicon-on-Insulator (SOI) -Halbleiterscheiben with a single crystalline substrate, a buried oxide layer and a semiconductor active layer, a plurality of mutually insulated by an insulator layer areas are provided with components in the active semiconductor layer above the buried oxide layer, wherein which perforations are in the insulator layer in the free of the active semiconductor layer regions introduced which up to the monocrystalline substrate, which are filled with a metal, whereby a metal filling is formed, and a passivation layer is formed with an opening over the area of ​​the metal filling on the insulator layer , and thereover a metal filling the overlying metallization layer is placed, and an electrical contact from the single crystalline substrate to the components in the active semiconductor layer is formed, characterized in that d ass mehrere Schichtenfolgen als Stapel aufgebracht werden, derart, dass zuerst eine Passivierungsschicht mit einer Öffnung über dem Bereich der Metallfüllung erzeugt wird, darüber eine die Metallfüllung überdeckende Metallisierungsschicht gelegt wird, wodurch die entsprechende Stelle des Substrats mit mehreren unterschiedlichen Schaltungspunkten der in der aktiven Halbleiterschicht liegenden Bauelemente elektrisch verbunden wird. ass a plurality of layer sequences are applied as a stack in such a way that first a passivation layer is formed with an opening over the area of ​​the metal filling, about a metal filling overlying metallization layer is placed, whereby the corresponding position of the substrate with a plurality of different circuit points of the lies in the active semiconductor layer components is electrically connected.
  2. Verfahren nach Anspruch 1, dadurch gekennzeichnet, dass die verschiedenen Passivierungs- und Metallschichten jeweils als Bestandteil der technologischen Schrittfolge bei der Herstellung der Metallisierungsebenen einer integrierten Schaltung mit erzeugt werden. The method of claim 1, characterized in that the various passivation and metal layers are formed in each case as part of the technological sequence of steps in the preparation of the metallization levels of an integrated circuit.
  3. Verfahren nach Anspruch 1, dadurch gekennzeichnet, dass die Passivierungsschicht eine Siliziumnitridschicht ist. A method according to claim 1, characterized in that the passivation layer is a silicon nitride layer.
  4. Verfahren nach Anspruch 1, dadurch gekennzeichnet, dass die Bedingungen an der Grenze Metall/Substrat so eingestellt werden, dass sich ein ohmscher Kontakt zum Substrat ausbildet. The method of claim 1, characterized in that the conditions at the metal / substrate are adjusted so that an ohmic contact to the substrate is formed.
  5. Verfahren nach Anspruch 1, dadurch gekennzeichnet, dass die Bedingungen an der Grenze Metall/Substrat so eingestellt werden, dass sich ein Schottky-Kontakt zum Substrat ausbildet. The method of claim 1, characterized in that the conditions at the metal / substrate are adjusted so that a Schottky contact with the substrate is formed.
DE2003103643 2003-01-30 2003-01-30 Electrical connection of active semiconductor structures with the substrate, at a silicon-on-insulator semiconductor wafer, has a passage opening through the insulating layer for a metal filling covered by a layered stack Active DE10303643B3 (en)

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Application Number Priority Date Filing Date Title
DE2003103643 DE10303643B3 (en) 2003-01-30 2003-01-30 Electrical connection of active semiconductor structures with the substrate, at a silicon-on-insulator semiconductor wafer, has a passage opening through the insulating layer for a metal filling covered by a layered stack

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
DE2003103643 DE10303643B3 (en) 2003-01-30 2003-01-30 Electrical connection of active semiconductor structures with the substrate, at a silicon-on-insulator semiconductor wafer, has a passage opening through the insulating layer for a metal filling covered by a layered stack
US10543896 US7485926B2 (en) 2003-01-30 2004-01-30 SOI contact structures
DE200411000646 DE112004000646D2 (en) 2003-01-30 2004-01-30 SOI contact structure (s) and manufacturing method thereof
EP20040706605 EP1595285A1 (en) 2003-01-30 2004-01-30 Soi contact structure(s) and corresponding production method
PCT/DE2004/000146 WO2004068574A1 (en) 2003-01-30 2004-01-30 Soi contact structure(s) and corresponding production method

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DE200411000646 Withdrawn - After Issue DE112004000646D2 (en) 2003-01-30 2004-01-30 SOI contact structure (s) and manufacturing method thereof

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005046624B3 (en) * 2005-09-29 2007-03-22 Atmel Germany Gmbh Production of semiconductor arrangement with formation of conductive substrate, structural element region (SER) layer for insulating SER from substrate useful in semiconductor technology, e.g. in production of DMOS-field effect transistors
DE102008034789B4 (en) * 2007-07-25 2010-02-04 Infineon Technologies Ag A method of manufacturing a semiconductor device, method for producing a SOI device, semiconductor device, and SOI device

Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5314841A (en) * 1993-04-30 1994-05-24 International Business Machines Corporation Method of forming a frontside contact to the silicon substrate of a SOI wafer
DE4314907C1 (en) * 1993-05-05 1994-08-25 Siemens Ag Method for producing semiconductor components making electrically conducting contact with one another vertically
DE4400985C1 (en) * 1994-01-14 1995-05-11 Siemens Ag Method for producing a three-dimensional circuit arrangement
DE4433846C2 (en) * 1994-09-22 1999-06-02 Fraunhofer Ges Forschung A process for producing a vertical integrated circuit structure
DE19904571C1 (en) * 1999-02-04 2000-04-20 Siemens Ag Three-dimensional IC, e.g. a DRAM cell array, is produced by electron beam passage through a substrate to locate an alignment structure in a bonded second substrate for mask alignment
GB2346260A (en) * 1999-01-28 2000-08-02 Ibm Forming trench contacts to substrates in SOI devices
DE4229628C2 (en) * 1991-09-10 2000-08-17 Mitsubishi Electric Corp A semiconductor device with stacked structure and methods for producing such
US6153912A (en) * 1999-10-25 2000-11-28 Advanced Micro Devices, Inc. SOI with conductive metal substrate used as VSS connection
US6188122B1 (en) * 1999-01-14 2001-02-13 International Business Machines Corporation Buried capacitor for silicon-on-insulator structure
DE10047963A1 (en) * 1999-09-28 2001-03-29 Sony Corp Making multilayer thin film component, assembles component units, each carrying component layers on supportive substrates
US6300666B1 (en) * 1998-09-30 2001-10-09 Honeywell Inc. Method for forming a frontside contact to the silicon substrate of a SOI wafer in the presence of planarized contact dielectrics
WO2001099180A2 (en) * 2000-06-16 2001-12-27 Advanced Micro Devices, Inc. Novel frontside contact to substrate of soi device
US6429477B1 (en) * 2000-10-31 2002-08-06 International Business Machines Corporation Shared body and diffusion contact structure and method for fabricating same
WO2002073667A2 (en) * 2001-03-14 2002-09-19 Honeywell International Inc. Formation of a frontside contact on silicon-on-insulator substrate

Patent Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4229628C2 (en) * 1991-09-10 2000-08-17 Mitsubishi Electric Corp A semiconductor device with stacked structure and methods for producing such
US5314841A (en) * 1993-04-30 1994-05-24 International Business Machines Corporation Method of forming a frontside contact to the silicon substrate of a SOI wafer
DE4314907C1 (en) * 1993-05-05 1994-08-25 Siemens Ag Method for producing semiconductor components making electrically conducting contact with one another vertically
DE4400985C1 (en) * 1994-01-14 1995-05-11 Siemens Ag Method for producing a three-dimensional circuit arrangement
DE4433846C2 (en) * 1994-09-22 1999-06-02 Fraunhofer Ges Forschung A process for producing a vertical integrated circuit structure
US6300666B1 (en) * 1998-09-30 2001-10-09 Honeywell Inc. Method for forming a frontside contact to the silicon substrate of a SOI wafer in the presence of planarized contact dielectrics
US6188122B1 (en) * 1999-01-14 2001-02-13 International Business Machines Corporation Buried capacitor for silicon-on-insulator structure
GB2346260A (en) * 1999-01-28 2000-08-02 Ibm Forming trench contacts to substrates in SOI devices
DE19904571C1 (en) * 1999-02-04 2000-04-20 Siemens Ag Three-dimensional IC, e.g. a DRAM cell array, is produced by electron beam passage through a substrate to locate an alignment structure in a bonded second substrate for mask alignment
DE10047963A1 (en) * 1999-09-28 2001-03-29 Sony Corp Making multilayer thin film component, assembles component units, each carrying component layers on supportive substrates
US6153912A (en) * 1999-10-25 2000-11-28 Advanced Micro Devices, Inc. SOI with conductive metal substrate used as VSS connection
WO2001099180A2 (en) * 2000-06-16 2001-12-27 Advanced Micro Devices, Inc. Novel frontside contact to substrate of soi device
US6429477B1 (en) * 2000-10-31 2002-08-06 International Business Machines Corporation Shared body and diffusion contact structure and method for fabricating same
WO2002073667A2 (en) * 2001-03-14 2002-09-19 Honeywell International Inc. Formation of a frontside contact on silicon-on-insulator substrate

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005046624B3 (en) * 2005-09-29 2007-03-22 Atmel Germany Gmbh Production of semiconductor arrangement with formation of conductive substrate, structural element region (SER) layer for insulating SER from substrate useful in semiconductor technology, e.g. in production of DMOS-field effect transistors
DE102008034789B4 (en) * 2007-07-25 2010-02-04 Infineon Technologies Ag A method of manufacturing a semiconductor device, method for producing a SOI device, semiconductor device, and SOI device
US7982281B2 (en) 2007-07-25 2011-07-19 Infineon Technologies Ag Method of manufacturing a semiconductor device, method of manufacturing a SOI device, semiconductor device, and SOI device

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