EP1595285A1 - Soi contact structure(s) and corresponding production method - Google PatentsSoi contact structure(s) and corresponding production method
- Publication number
- EP1595285A1 EP1595285A1 EP20040706605 EP04706605A EP1595285A1 EP 1595285 A1 EP1595285 A1 EP 1595285A1 EP 20040706605 EP20040706605 EP 20040706605 EP 04706605 A EP04706605 A EP 04706605A EP 1595285 A1 EP1595285 A1 EP 1595285A1
- Grant status
- Patent type
- Prior art keywords
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
SOI-contact structure (s) and manufacturing method thereof
The invention relates to SOI structures (Silicon-on-Insulator) in which electrical connections between device structures are made in the upper insulated from the substrate semiconductor layer and the semiconductor substrate, which pass through the insulator layer to the upper semiconductor layer.
An SOI structure consisting of a thin semiconductor layer which is located on a thin oxide layer. The oxide layer is commonly referred to as buried oxide (buried oxide BOX) is generated and in turn lies on a semiconductor layer, generally a silicon layer, namely the silicon substrate, which usually has a thickness of 300 to 800 .mu.m. This substrate is only used for handling of the structure. The actual components functions are implemented as in conventional CMOS processes on homogenous silicon wafers in the near-surface semiconductor layer.
An essential difference with standard CMOS processes is that the components are dielectrically isolated from each other by trenches which extend up to the insulating layer. In this way, the mutual electrical interaction of the components is greatly reduced. This dielectric isolation makes the SOI technology for high-voltage applications.
On the one hand it provides advantages when the components are not coupled to each other over the substrate. It thus eliminating the substrate certain undesirable effects such as latch-up, significant reverse currents at elevated
Temperatures, increased parasitic capacitances of the source / bulk or drain / bulk pn junctions. On the other hand it provides advantages if a substrate compound is to be able to include, for example certain generated in the substrate active or passive structures in the circuit. In this way, components of other non-SOI technology appropriate procedures are integrated. Electrical connections to the substrate would be advantageous. However, the back-side of the substrate used therefor is not part of the SOI technology. see the corresponding housing a rear-side contact not before and often the number of pins is not sufficient for circuits to perform the back contact or such contact to the outside. The object of the invention is to provide an electrical connection of SOI device structures in a silicon active layer with the substrate by bypassing or avoiding a back-side of the substrate. Here, the degree of integration of circuits should be increased. Other than the SOI technology corresponding elements are to be included.
The inventive solution is circumscribed in the characterizing part of claim 1 or 7, or with the features of claims 11 or twentieth Further embodiments of the invention are contained in the subclaims.
One implementation provides a connection of active structures on the top surface to the substrate in this manner. This can be easily carried out one or more times, such as in the claimed layer stack such that different component groups on the upper side can be connected to the substrate separately.
Also, a combination of upper-side component structures with doped regions in the substrate is possible.
On the insulator layer of the SOI wafer, at least one layer sequence consisting applied each consisting of two layers.
Of the layers a first passivation layer is provided with an opening over the metal filling, over which lies a second layer as a metallization layer, which is conductively connected to the metal filler and electrical contact or lead structure to the substrate prepared in order prepared at the front of SOI structures to connect to the substrate to contact or conductive.
Repeat several times results in a sequence of respectively a passivation layer which has an opening over the area of the metal filling, and each having a metallization layer overlying the passivation layer and the area of the metal filling.
Electrical contact is made between the substrate and of prepared on the wafer front side structures, so that the stack of several alternating metal and passivation layers having different conductive level layers which have a different distance from the insulator layer. illustrate embodiments and supplement the invention, wherein like reference numerals describe like elements.
Figure 1 illustrates a first embodiment in which a contacting a substrate with a layer stack is performed.
Figure 2 illustrates the embodiment of Figure 1 with illustrative reference numerals.
Figure 3 illustrates a further embodiment, also showing the separate lateral compound on the substrate, above the insulating layer 11 starting from the first metallization 70. The active structures on the top side are here schematically at 40 and 50 shown, and were showing a substrate contact in Figure 1 not shown separately.
serves to explain the invention in Figure 1, it shows schematically the contacting of the substrate with a layer stack.
The execution establishes a connection of the active structures on the top surface to the substrate in this manner. This can be easily carried out one or more times, as in the example shown in Fig.1 stack so that different device groups on the upper side can be connected to the substrate separately. The connection of the upper-side component structures with doped regions in the substrate is possible.
With the indicated in the figure 1 designations it is self-explanatory and needs no further explanation.
creating a contact at the interfaces between the metal of the implementation and the substrate. This may be an ohmic contact or a Schottky contact. Both species are of technical importance and can be adjusted purposefully.
Contacting the substrate according to Figure 1 also shows the figure 3. The embodiment is identical. The added characters are taken with respect to give a more detailed explanation of the layer stack, which is located in each execution 19,20. The contacting of the substrate takes place as well as the figure 1 through the stack of layers 80, which consists of several layers, in example, six layers. The feed-through 20 is a metallic filling a hole or the opening 19 in the insulator layer 11 which is the subject of a SOI wafer 10. The substrate 13 supports the insulator 11, for example as a BOX layer. Above the insulator 11, a semiconductor layer is already patterned represented 12, which is shown in the left and right edge region as a structured residual layer 12 'and 12 "for at least partial inclusion of active devices is. These components are symbolically denoted by 40 and 50 and located to the left and right of the layer stack 80, which is arranged in a region which is free from the monocrystalline semiconductor layer 12th this region is denoted by 12a, wherein the entire single crystal semiconductor layer 12, by patterning in this area, the free from this layer region 12a the remaining layers 12 'and 12 "is obtained.
The implementation 19 as, for example, an etched feedthrough hole is filled with a mass of metal to create a metal layer (or a metal plug "plug") that closes upward and downward with the insulator layer substantially or rests touching down on the substrate layer. 13
The implementation thus provides a connection of active structures 40,50 on the upper side (front side V) of the SOI wafer to the substrate 13 which has a rear side R.
This implementation can be easily carried out one or more times, as in the example shown in Figure 1 pile. Thus, different component groups on the upper side can be connected separately to the substrate. different
Components (or groups) can also be connected to the same Through Hole and the conductive connection 20 or in order to conductively connect a plurality of components with the same substrate at the same site implementation 19/20.
Doping regions may be provided - can on the surface of the substrate in the lead-through opening 19 - which is not shown separately. If no doping region is provided, a Schottky contact forms 13c, as illustrated in FIG. 2 In a doped region with p-type or n-type doping an ohmic contact to the substrate 13. This interface region forms is called the "interface" between the metal of the implementation and the substrate.
The layer sequence 30 to 32 and nested within 70 to 72 will be explained in the following. In a manufacturing process, the stacked structure of layers is shown in Figure 2. The substrate contact 20 is guided to the front side and in layers built up there in order to be able to contact him metallic in different planes at different heights and distances from the insulating layer. 11 These various layers are each spaced apart by a thickness of a passivation layer 70,71, 72, which are arranged alternately in the stack, and have a passage opening through which the metallic lead structure 20, so that a central of the metallization layers 70,71, 72 is reached or internal passage through the stack results, which lies above the passage opening 19 and is completely electrically conductively filled metallic.
At locations which are free of the active semiconductor layer 12, so the trench 12a, the insulator layer is provided with the through Hole 19, which extends up to the substrate 13, in particular by etching. A plurality of holes can be spaced and substantially at the same time etched.
A metal bushing 20 is generated by filling the respective penetration hole 19th It concludes with the insulator layer.
Above the metal duct 20 a perforated passivation layer 30 is applied as the first passivation, which has a lateral extension and rests on the insulator. 11 In a further process step, a metal layer 70 is placed which extends through the perforated passivation layer on the breakthrough and is electrically conductive, the metal layer 20 contacts in the Through Hole, as shown at 70a. The contact point 20a has a depression corresponding substantially to the shape or dimension of the aperture through the passivation layer 30th
Optionally, the first metal layer 70 may be patterned to make electrical contact within the range of component structures. This illustrates the lateral interconnect 70a, starting from the first metallization 70, Figure 3 as a further embodiment. The laterally extending conductive line 70a reaches the 'prepared in the active semiconductor layer 12 structure 40. This lateral connection extending on the first plane (elevation plane) above the surface of the insulator layer 11. A further passivation layer 31 is applied to the metallization 70 and also by broken as already the first passivation 30th
The result of layer pairs from each passivation and metallization described can be continued several times. Thus, the second passivation 31 and the second metallization 71. A third passivation 32 and a third metallization 72 can follow, as illustrated in FIG. 2
Each broken through the passivation in the region above the metallic feed-through 20, for forming a central or inner core of metallic material for conductive connection and the top metallization layer 72 is 13c to the substrate 13 or to ohmic or Schottky contact.
In lateral direction, the passivation layers are each reduced more, the further they are away from the insulator layer. 11 The stack tapers upwards, as can be seen in section in FIGS. 1 to 3
In Figure 3, in another embodiment, a metal web, adopted is shown 72b on the third level, which over sufficient to further prepared structure 50 in the active semiconductor layer 12 "and then makes an electrical contact, as already laterally extending conductor path 70a to the first prepared structure 40 at the lowest height level.
The various electrical paths are merged on the stacked metallization and of different levels, in order together to contact electrically conductive by the implementation of a 19/20 to the substrate. 13
In a plan view, the described structures, in particular the stack structure 80 is not round in its outer extent, preferably rectangular or square are.
Several of the stacked structures described may be arranged in regions which are free from the active semiconductor layer, and correspond to the "ditch" 12 respectively.
Priority Applications (3)
|Application Number||Priority Date||Filing Date||Title|
|DE2003103643 DE10303643B3 (en)||2003-01-30||2003-01-30||Electrical connection of active semiconductor structures with the substrate, at a silicon-on-insulator semiconductor wafer, has a passage opening through the insulating layer for a metal filling covered by a layered stack|
|PCT/DE2004/000146 WO2004068574A1 (en)||2003-01-30||2004-01-30||Soi contact structure(s) and corresponding production method|
|Publication Number||Publication Date|
|EP1595285A1 true true EP1595285A1 (en)||2005-11-16|
Family Applications (1)
|Application Number||Title||Priority Date||Filing Date|
|EP20040706605 Withdrawn EP1595285A1 (en)||2003-01-30||2004-01-30||Soi contact structure(s) and corresponding production method|
Country Status (3)
|US (1)||US7485926B2 (en)|
|EP (1)||EP1595285A1 (en)|
|WO (1)||WO2004068574A1 (en)|
Families Citing this family (4)
|Publication number||Priority date||Publication date||Assignee||Title|
|EP1595285A1 (en) *||2003-01-30||2005-11-16||X-FAB Semiconductor Foundries AG||Soi contact structure(s) and corresponding production method|
|DE102005046624B3 (en) *||2005-09-29||2007-03-22||Atmel Germany Gmbh||Production of semiconductor arrangement with formation of conductive substrate, structural element region (SER) layer for insulating SER from substrate useful in semiconductor technology, e.g. in production of DMOS-field effect transistors|
|DE102007016257A1 (en)||2007-04-04||2008-10-09||X-Fab Semiconductor Foundries Ag||A method for manufacturing an electrical contact carrier disc with front connection|
|US7982281B2 (en) *||2007-07-25||2011-07-19||Infineon Technologies Ag||Method of manufacturing a semiconductor device, method of manufacturing a SOI device, semiconductor device, and SOI device|
Family Cites Families (23)
|Publication number||Priority date||Publication date||Assignee||Title|
|US5241211A (en) *||1989-12-20||1993-08-31||Nec Corporation||Semiconductor device|
|US5479048A (en) *||1994-02-04||1995-12-26||Analog Devices, Inc.||Integrated circuit chip supported by a handle wafer and provided with means to maintain the handle wafer potential at a desired level|
|US5665622A (en) *||1995-03-15||1997-09-09||International Business Machines Corporation||Folded trench and rie/deposition process for high-value capacitors|
|US5610083A (en) *||1996-05-20||1997-03-11||Chartered Semiconductor Manufacturing Pte Ltd||Method of making back gate contact for silicon on insulator technology|
|CA2233096C (en) *||1997-03-26||2003-01-07||Canon Kabushiki Kaisha||Substrate and production method thereof|
|US6191007B1 (en) *||1997-04-28||2001-02-20||Denso Corporation||Method for manufacturing a semiconductor substrate|
|US6124615A (en) *||1998-05-04||2000-09-26||United Microelectronics Corp.||Stacked semiconductor structure for high integration of an integrated circuit with junction devices|
|JP2000012868A (en)||1998-06-23||2000-01-14||Toshiba Corp||Semiconductor device and manufacture thereof|
|US6272736B1 (en) *||1998-11-13||2001-08-14||United Microelectronics Corp.||Method for forming a thin-film resistor|
|JP4437570B2 (en) *||1999-07-12||2010-03-24||株式会社ルネサステクノロジ||The method of manufacturing a semiconductor device and a semiconductor device|
|KR100344220B1 (en) *||1999-10-20||2002-07-19||삼성전자 주식회사||semiconductor device having SOI structure and method for fabricating the same|
|US6303414B1 (en) *||2000-07-12||2001-10-16||Chartered Semiconductor Manufacturing Ltd.||Method of forming PID protection diode for SOI wafer|
|JP2002190521A (en) *||2000-10-12||2002-07-05||Oki Electric Ind Co Ltd||Method for fabricating semiconductor device|
|US6603166B2 (en)||2001-03-14||2003-08-05||Honeywell International Inc.||Frontside contact on silicon-on-insulator substrate|
|JP3589997B2 (en) *||2001-03-30||2004-11-17||株式会社東芝||Infrared sensor and its manufacturing method|
|EP1595285A1 (en) *||2003-01-30||2005-11-16||X-FAB Semiconductor Foundries AG||Soi contact structure(s) and corresponding production method|
|JP2005109346A (en) *||2003-10-01||2005-04-21||Seiko Epson Corp||Semiconductor device and method of manufacturing semiconductor device|
|US7612416B2 (en) *||2003-10-09||2009-11-03||Nec Corporation||Semiconductor device having a conductive portion below an interlayer insulating film and method for producing the same|
|JP2005175090A (en) *||2003-12-09||2005-06-30||Toshiba Corp||Semiconductor memory device and its manufacturing method|
|US7279375B2 (en) *||2005-06-30||2007-10-09||Intel Corporation||Block contact architectures for nanoscale channel transistors|
|US20080048186A1 (en) *||2006-03-30||2008-02-28||International Business Machines Corporation||Design Structures Incorporating Semiconductor Device Structures with Self-Aligned Doped Regions|
|US7898014B2 (en) *||2006-03-30||2011-03-01||International Business Machines Corporation||Semiconductor device structures with self-aligned doped regions and methods for forming such semiconductor device structures|
|US7718503B2 (en) *||2006-07-21||2010-05-18||Globalfoundries Inc.||SOI device and method for its fabrication|
Non-Patent Citations (1)
|See references of WO2004068574A1 *|
Also Published As
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|US5807783A (en)||Surface mount die by handle replacement|
|US6844241B2 (en)||Fabrication of semiconductor structures having multiple conductive layers in an opening|
|US6632710B2 (en)||Method for forming semiconductor device|
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|US20040262767A1 (en)||Semiconductor device|
|US7053453B2 (en)||Substrate contact and method of forming the same|
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|US5569621A (en)||Integrated circuit chip supported by a handle wafer and provided with means to maintain the handle wafer potential at a desired level|
|US20110241185A1 (en)||Signal shielding through-substrate vias for 3d integration|
|US5449946A (en)||Semiconductor device provided with isolation region|
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|US5932917A (en)||Input protective circuit having a diffusion resistance layer|
|US6693325B1 (en)||Semiconductor device having silicon on insulator and fabricating method therefor|
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