JPH02290058A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enhance the driving capacity by a method wherein two each of conductive layers for power supply line are contained in the grooves provided on the semiconductor substrate of a semiconductor integrated circuit containing a large power driving transistor(Tr) without increasing the area occupied by a power supply substrate from the driving Tr. CONSTITUTION:Conductive layers 190 for power supply line are formed through dielectric isolation from a P-type silicon substrate 11 of a semiconductor integrated circuit in the grooves provided on the substrate 11 through the intermediary of silicon oxide films 15. Besides, the other conductive layers 191 for power supply line are also formed through dielectric isolation from the conductive layers 190 on the layers 190 in the grooves 20 provided on the substrate 11 so as to be buried in the grooves 20 through the intermediary of the oxide films 15. Then, gate electrodes 12 of CMOS driving transistor(Tr) element, N-type diffused layers 16, an N well 17 and P type diffused layers 18 are respectively formed. In such a constitution, the driving capacity of the semiconductor integrated circuit in increased conductive capacity can be enhanced so that the power supply from the driving Tr element containing the conductive layers 190, 191 may not increase the occupied area by the substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit including a high power drive transistor.

[Conventional technology]

FIGS. 2(a) and 2(b) are a partial plan view and a schematic cross-sectional view taken along the line Y--Y' of the conventional semiconductor integrated circuit.

The signal line conductive layer M23 and the power line conductive layer 29 are formed so as to extend on the P-type silicon substrate 21 via the silicon oxide film 25, respectively. Here, a complementary MOS transistor (hereinafter referred to as a CMOS transistor) is constructed by an N-type diffusion layer 26 and a P-type diffusion layer 28 which are provided in the region of the P-type silicon substrate 21 and the N-well 27 in conjunction with the gate electrode 22. are doing.

[Problem to be solved by the invention]

In the conventional semiconductor integrated circuits mentioned above, there has recently been a demand for increased drive capability with large currents, and along with this, it is necessary to thicken the conductive layer for the power supply line or increase the line width, resulting in an increase in the area occupied by the substrate. The increase became noticeable. However, if the vertical thickness is increased, the power line conductive layer 291
Since the conductive layer 24 for the signal line that crosses the top of the chip has a step or curve, it is easy for wire breakage to occur.Although increasing the width in the lateral direction can prevent the occurrence of wire breakage, Increase the size.

Also, conductive wire WI2 for power supply line to supply to the drive transistor element.
90,291. Is a conductive W only for power supply by design! 29029
] If the layout is reversed, it will be necessary to route the wiring to that point, increasing the chip size and making it difficult to achieve high integration.

An object of the present invention is to provide a semiconductor integrated circuit including a conductive layer for a power supply line with a large current capacity that improves the reliability and high integration of the conductive layer for a signal line.

[Means to solve the problem]

A semiconductor integrated circuit of the present invention includes a semiconductor substrate, a drive transistor element formed on the semiconductor substrate, and a signal line conductive layer and a power line conductive layer disposed around the transistor element. The conductive layer for the power supply line is insulated and separated from the semiconductor substrate by a first insulating film, and is insulated from the semiconductor substrate by a second insulating film, and is insulated from the semiconductor substrate in a region provided on the semiconductor substrate near the transistor element formation region. It is formed into two layers.

〔Example〕

Next, FIG. 1 (
a). (b) is a partial plan view of one embodiment of the present invention and a schematic cross-sectional view taken along the line xx'.

Figure 1(a). As shown in (b), in the semiconductor integrated circuit of the present invention, a conductive layer 190 for a power supply line is formed on a P-type silicon substrate 1.
Ko ten. A silicon oxide film 5 is formed in the groove 20 provided in the silicon substrate 1-1 to be insulated and isolated from the silicon substrate 1-1. The conductive layer 191 for the power supply line is a groove 20 provided on a P-type silicon substrate]
A silicon oxide film 15 is formed on the conductive layer 190 for the power supply line inside the
Through the conductive layer 190 for the source line and insulated and separated from the conductive layer 190.
Form to fill. 12.16.17 and 18 are gate electrodes of C-MOS drive transistor elements;
An N-type diffusion layer, an N-well, and a P-type diffusion layer are shown, respectively, and a CMOS transistor is constructed in the same manner as in the conventional example. In such a wiring structure in which a conductive film layer for a power line is housed within a substrate, the conductive film thickness or film layer width can be set large regardless of other horizontal structures on the board in order to withstand large current drive. . Furthermore, since there are always different conductive film layers for power supply lines, supply can be easily performed without worrying about the position and direction of the drive transistor.

〔Effect of the invention〕

As explained above, according to the present invention, a conductive layer for power supply lines consisting of at least two wires is housed in a groove provided in a semiconductor substrate, so that the power supply from the drive transistor can be increased in current carrying capacity without expanding the area occupied by the substrate. Therefore, it is possible to extremely easily achieve high integration of semiconductor integrated circuits with extremely large driving capabilities.

Figures (a) and (b) are a partial plan view of a conventional semiconductor integrated circuit and a schematic cross-sectional view taken along the line Y-Y'.

1]. ．． 2].・・P-type silicon substrate, 1.2.22・
Gate electrode, 1.3, 23, 1.4. , 2/I
...Conductive layer for signal line, 15,25...Silicon oxide film, 1626...N type diffusion layer, 17.27...N well, 18,2 s -. - p-type diffusion layer, ]-90.1.
91. 290 291-- Conductive layer for power supply line,
2o...groove.

Agent: Patent Attorney: Shu Uchihara

[Brief explanation of drawings]

Claims (1)

[Claims] In a semiconductor integrated circuit having a complementary MOS transistor provided on one main surface of a semiconductor substrate, a groove provided in the semiconductor substrate near the complementary transistor, an insulating film provided on an inner surface of the groove, a first conductive layer provided on the surface of the first insulating film; a second insulating film provided on the surface of the first conductive layer; and a second conductive layer provided on the surface of the second insulating film.
A semiconductor integrated circuit comprising a conductive layer to form a power supply wiring for the complementary transistor.