JPH0345898B2 - - Google Patents
Info
- Publication number
- JPH0345898B2 JPH0345898B2 JP59125763A JP12576384A JPH0345898B2 JP H0345898 B2 JPH0345898 B2 JP H0345898B2 JP 59125763 A JP59125763 A JP 59125763A JP 12576384 A JP12576384 A JP 12576384A JP H0345898 B2 JPH0345898 B2 JP H0345898B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- semiconductor
- polysilicon layer
- channel transistor
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 74
- 239000010410 layer Substances 0.000 claims description 43
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 34
- 229920005591 polysilicon Polymers 0.000 claims description 34
- 239000000758 substrate Substances 0.000 claims description 34
- 239000004020 conductor Substances 0.000 claims description 16
- 239000002344 surface layer Substances 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 230000003071 parasitic effect Effects 0.000 description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体集積回路装置のボンデイン
グパツドの構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a bonding pad for a semiconductor integrated circuit device.
従来、Ｃ−MOSIOなどの半導体集積回路装置
では、第３図および第４図に示すように、半導体
基板２の表面層に半導体基板２とは反対導電形の
半導体領域４が形成されており、この半導体領域
４を覆つて酸化膜（たとえばSiO2膜）６が形成
され、その表面にアルミニウムなどの配線導体８
が設置されている。
Conventionally, in a semiconductor integrated circuit device such as C-MOSIO, as shown in FIGS. 3 and 4, a semiconductor region 4 of the opposite conductivity type to that of the semiconductor substrate 2 is formed in the surface layer of the semiconductor substrate 2. An oxide film (for example, SiO 2 film) 6 is formed covering this semiconductor region 4, and a wiring conductor 8 made of aluminum or the like is formed on its surface.
is installed.
この配線導体８は絶縁層１０で覆われており、
この配線導体８と一体的にボンデイング用パツド
部１２が形成されている。１４は絶縁層１０に形
成された開口である。 This wiring conductor 8 is covered with an insulating layer 10,
A bonding pad portion 12 is formed integrally with this wiring conductor 8. 14 is an opening formed in the insulating layer 10.
ボンデイング用パツド部１２には、図示してい
ないピンを電気的に接続するための金線などの導
電性ワイヤ１６が溶着されている。 A conductive wire 16 such as a gold wire is welded to the bonding pad portion 12 for electrically connecting a pin (not shown).
このようなボンデイングパツド構造では、次の
ような問題点がある。
Such a bonding pad structure has the following problems.
配線導体８と半導体領域４との間の静電容
量、あるいは配線導体８と半導体基板２との間
に存在する寄生容量が、半導体集積回路の入出
力に著しく影響を与える。 The electrostatic capacitance between the wiring conductor 8 and the semiconductor region 4 or the parasitic capacitance existing between the wiring conductor 8 and the semiconductor substrate 2 significantly influences the input/output of the semiconductor integrated circuit.
酸化膜６の表面に水分などの不純物が存在し
ている場合、酸化膜６と配線導体８との接合強
度が低下するおそれがある。 If impurities such as moisture are present on the surface of the oxide film 6, the bonding strength between the oxide film 6 and the wiring conductor 8 may be reduced.
酸化膜６は非常に硬く、ワイヤボンデイング
時の衝撃によつて破損し、半導体基板２との絶
縁性が低下するおそれがある。 The oxide film 6 is very hard and may be damaged by impact during wire bonding, resulting in a decrease in insulation with the semiconductor substrate 2.
そこで、この発明は、配線導体と半導体基板と
の間における寄生容量の影響を軽減するととも
に、ワイヤボンデイング時の衝撃による酸化膜の
破損を防止し、かつ配線導体の密着強度を高めた
半導体集積回路装置の提供を目的とする。 SUMMARY OF THE INVENTION Accordingly, the present invention provides a semiconductor integrated circuit that reduces the influence of parasitic capacitance between a wiring conductor and a semiconductor substrate, prevents damage to the oxide film due to impact during wire bonding, and increases the adhesion strength of the wiring conductors. The purpose is to provide equipment.
即ち、この発明の半導体集積回路装置は、半導
体基板２０の表面層にＮチヤンネルトランジスタ
２８及びＰチヤンネルトランジスタ３０を形成し
た半導体集積回路装置において、前記Ｎチヤンネ
ルトランジスタ及びＰチヤンネルトランジスタに
隣接し、これらトランジスタの形成域より僅かに
窪ませた前記半導体基板の表面層に設置され、前
記半導体基板と反対導電形を成す半導体領域２４
と、この半導体領域を覆つて設置されて前記半導
体基板の表面を被覆する酸化膜２６と、この酸化
膜の表面に選択的に形成されたポリシリコン層４
４と、前記Ｎチヤンネルトランジスタ及びＰチヤ
ンネルトランジスタの各ゲートに接続されている
とともに、前記ポリシリコン層の上面に設置され
た配線導体から成るボンデイング用接続部５６
と、このボンデイング用接続部に接続された導電
性ワイヤ６６と、前記ボンデイング用接続部を覆
う絶縁層６０とを備え、前記半導体領域と前記ポ
リシリコン層との間に前記酸化膜を挟んで形成さ
れた静電容量と、前記半導体基板と前記半導体領
域との接合で形成された接合容量と前記ポリシリ
コン層による高抵抗とからなるインピーダンス回
路を前記ボンデイング用接続部と前記半導体領域
との間に介在させてなるものである。
That is, in the semiconductor integrated circuit device of the present invention, in a semiconductor integrated circuit device in which an N-channel transistor 28 and a P-channel transistor 30 are formed on the surface layer of a semiconductor substrate 20, the transistors are adjacent to the N-channel transistor and the P-channel transistor. A semiconductor region 24 is installed in the surface layer of the semiconductor substrate slightly recessed from the formation area, and has a conductivity type opposite to that of the semiconductor substrate.
, an oxide film 26 disposed to cover the semiconductor region and covering the surface of the semiconductor substrate, and a polysilicon layer 4 selectively formed on the surface of the oxide film.
4, and a bonding connection portion 56 which is connected to each gate of the N-channel transistor and the P-channel transistor and is made of a wiring conductor and is placed on the upper surface of the polysilicon layer.
, a conductive wire 66 connected to the bonding connection part, and an insulating layer 60 covering the bonding connection part, and formed by sandwiching the oxide film between the semiconductor region and the polysilicon layer. an impedance circuit consisting of a capacitance formed by the bonding, a junction capacitance formed by the junction between the semiconductor substrate and the semiconductor region, and a high resistance due to the polysilicon layer, between the bonding connection portion and the semiconductor region. This is done through intervention.
この発明の半導体集積回路装置では、酸化膜の
表面に多結晶絶縁層としてのポリシリコン層を介
在させて配線導体を設置したので、そのポリシリ
コン層による高抵抗がボンデイング用接続部と半
導体基板との間に設置されて高インピーダンス化
が図られることにより、ボンデイング用接続部と
半導体基板との間に存在する寄生容量の影響が低
減するとともに、高周波特性が改善される。ま
た、ポリシリコン層は、弾力性を備えているため
緩衝体として作用するので、ワイヤボンデイング
時の衝撃から酸化膜を保護し、また、酸化膜や配
線導体との高い密着性などにより、酸化膜と配線
導体との間に結合強度を向上させる。
In the semiconductor integrated circuit device of the present invention, since the wiring conductor is installed with a polysilicon layer as a polycrystalline insulating layer interposed on the surface of the oxide film, the high resistance due to the polysilicon layer connects the bonding connection and the semiconductor substrate. By providing a high impedance between the bonding connection portion and the semiconductor substrate, the influence of parasitic capacitance existing between the bonding connection portion and the semiconductor substrate is reduced, and high frequency characteristics are improved. In addition, the polysilicon layer has elasticity and acts as a buffer, protecting the oxide film from impact during wire bonding. and the wiring conductor to improve the bonding strength.
以下、この発明を図面に示した実施例を参照し
て詳細に説明する。
Hereinafter, the present invention will be described in detail with reference to embodiments shown in the drawings.
第１図はこの発明の半導体集積回路装置の実施
例を示し、この実施例はＮチヤンネルおよびＰチ
ヤンネルトランジスタを形成した半導体集積回路
について示したものである。 FIG. 1 shows an embodiment of a semiconductor integrated circuit device of the present invention, and this embodiment shows a semiconductor integrated circuit in which N-channel and P-channel transistors are formed.
Ｎ形半導体またはＰ形半導体で形成された半導
体基板２０の表面層には、半導体基板２０とは反
対導電形の半導体領域２２，２４が形成されてい
る。半導体領域２４は、半導体基板２０の表面層
に隣接して形成されたＮチヤンネルトランジスタ
２８およびＰチヤンネルトランジスタ３０の形成
域より僅かに窪ませた半導体基板２０の表面層に
設置されている。そして、半導体基板２０の表面
には、選択的に表面を覆う酸化膜２６が形成さ
れ、この酸化膜２６によつて半導体領域２４が覆
われている。 Semiconductor regions 22 and 24 of a conductivity type opposite to that of the semiconductor substrate 20 are formed in the surface layer of the semiconductor substrate 20 made of an N-type semiconductor or a P-type semiconductor. The semiconductor region 24 is provided in the surface layer of the semiconductor substrate 20, which is slightly recessed from the formation area of the N-channel transistor 28 and the P-channel transistor 30, which are formed adjacent to the surface layer of the semiconductor substrate 20. An oxide film 26 is formed on the surface of the semiconductor substrate 20 to selectively cover the surface, and the semiconductor region 24 is covered with this oxide film 26.
そして、Ｎチヤンネルトランジスタ２８および
Ｐチヤンネルトランジスタ３０が形成されている
半導体基板２０の表面層を覆う酸化膜２６には、
選択的に開口６２が形成され、その開口６２より
半導体基板２０とは反対導電形の半導体領域３
２，３４を形成するとともに、半導体領域２２に
は半導体基板２０と同一導電形の半導体領域３
６，３８がＰ形不純物またはＮ形不純物の拡散に
よつて形成されている。 The oxide film 26 covering the surface layer of the semiconductor substrate 20 on which the N-channel transistor 28 and the P-channel transistor 30 are formed has
An opening 62 is selectively formed, and the semiconductor region 3 having a conductivity type opposite to that of the semiconductor substrate 20 is formed through the opening 62.
2 and 34, and a semiconductor region 3 having the same conductivity type as the semiconductor substrate 20 is formed in the semiconductor region 22.
6 and 38 are formed by diffusion of P-type impurities or N-type impurities.
また、各トランジスタ２８，３０のゲート形成
部分および半導体領域２４を覆う酸化膜２６の部
分には、多結晶絶縁層としてのポリシリコン層４
０，４２，４４がそれぞれ設置され、これらは製
造上、同時に形成する。 In addition, a polysilicon layer 4 as a polycrystalline insulating layer is provided in a portion of the oxide film 26 covering the gate forming portion of each transistor 28, 30 and the semiconductor region 24.
0, 42, and 44 are installed, respectively, and these are formed at the same time in manufacturing.
ポリシリコン層４０の上面にはトランジスタ２
８のゲート４６、また、ポリシリコン層４２の上
面にはトランジスタ３０のゲート４８がアルミニ
ウムなどで形成されるとともに、半導体領域３２
には配線導体５０、半導体領域３４，３６を接続
する配線導体５２、半導体領域３８には配線導体
５４、ポリシリコン層４４を覆う位置にはボンデ
イング用接続部５６が形成される。接続部５６
は、各トランジスタ２８，３０の共通のゲート用
パツドを形成している。 A transistor 2 is provided on the upper surface of the polysilicon layer 40.
In addition, the gate 48 of the transistor 30 is formed of aluminum or the like on the upper surface of the polysilicon layer 42, and the gate 48 of the transistor 30 is formed on the upper surface of the polysilicon layer 42.
A wiring conductor 50 , a wiring conductor 52 connecting the semiconductor regions 34 and 36 , a wiring conductor 54 in the semiconductor region 38 , and a bonding connection portion 56 at a position covering the polysilicon layer 44 are formed. Connection part 56
forms a common gate pad for each transistor 28,30.
各ゲート４６，４８は、破線５８で示す配線導
体によつて電気的に接続されているとともに、そ
の上面部は絶縁層６０で被覆されている。 Each of the gates 46 and 48 is electrically connected by a wiring conductor indicated by a broken line 58, and the upper surface thereof is covered with an insulating layer 60.
そして、絶縁層６０のポリシリコン層４４を覆
う部分に開口６２が形成され、ワイヤボンデイン
グ用接続部５６の表面が露出している。この接続
部５６には、ピンとの間を電気的に接続するため
の導電性ワイヤ６６が溶接により固着されてい
る。 An opening 62 is formed in a portion of the insulating layer 60 that covers the polysilicon layer 44, and the surface of the wire bonding connection portion 56 is exposed. A conductive wire 66 for electrically connecting to the pin is fixed to this connecting portion 56 by welding.
このように構成すれば、導電性ワイヤ６６を接
続するボンデイング用接続部５６と酸化膜２６と
の間に設置されたポリシリコン層４４は高抵抗を
呈する。 With this configuration, the polysilicon layer 44 provided between the bonding connection portion 56 to which the conductive wire 66 is connected and the oxide film 26 exhibits high resistance.
ところで、このようなポリシリコン層４４を設
置しない場合には、第２図のＡに示すように、ボ
ンデイング用接続部５６と半導体領域２４との間
に酸化膜２６を挟んで形成される静電容量C1と、
半導体領域２４と半導体基板２０との接合によつ
て形成される接合容量C2とからなる寄生容量Ｃ
が、ボンデイング用接続部５６と半導体基板２０
との間に寄生することになる。この寄生容量Ｃの
容量値は、Ｃ＝C1・C2／（C1＋C2）となり、静
電容量C1、接合容量C2に対してその大小関係は
Ｃ＜C1、Ｃ＜C2となり、極めて小さい値となる。
この寄生容量Ｃのため、高周波特性が悪化するの
である。 By the way, if such a polysilicon layer 44 is not provided, as shown in A of FIG. Capacity C 1 and
A parasitic capacitance C consisting of a junction capacitance C 2 formed by the junction between the semiconductor region 24 and the semiconductor substrate 20
However, the bonding connection portion 56 and the semiconductor substrate 20
It will become parasitic between. The capacitance value of this parasitic capacitance C is C=C 1・C 2 /(C 1 +C 2 ), and the magnitude relationship with respect to electrostatic capacitance C 1 and junction capacitance C 2 is C<C 1 and C<C 2 , which is an extremely small value.
This parasitic capacitance C deteriorates the high frequency characteristics.
そこで、ポリシリコン層４４を設置した場合に
は、ポリシリコン層４４による高抵抗をＲとする
と、ボンデイング用接続部５６と半導体基板２０
との間には、第２図のＢに示すように、静電容量
C1と接合容量C2とからなる寄生容量Ｃに高抵抗
Ｒを直列に接続したインピーダンス回路を挿入し
たことになる。このインピーダンス回路が持つイ
ンピーダンス値に対して高抵抗Ｒの占める割合が
大きく、高抵抗Ｒの付加により、寄生容量Ｃの影
響を低減することができる。この結果、シリコン
ゲートMOSトランジスタにおける高周波特性が
大幅に改善されるのである。 Therefore, when the polysilicon layer 44 is installed, if the high resistance due to the polysilicon layer 44 is R, the bonding connection part 56 and the semiconductor substrate 20
As shown in B in Figure 2, there is a capacitance between
This means that an impedance circuit is inserted in which a high resistance R is connected in series to a parasitic capacitance C consisting of C1 and a junction capacitance C2 . The high resistance R occupies a large proportion of the impedance value of this impedance circuit, and by adding the high resistance R, the influence of the parasitic capacitance C can be reduced. As a result, the high frequency characteristics of silicon gate MOS transistors are significantly improved.
ポリシリコン層４４をポリシリコンで形成する
場合、ゲート４６，４８の部分に設置するポリシ
リコン層と同時に設置でき、特別な工程を必要と
しない。 When the polysilicon layer 44 is formed of polysilicon, it can be formed at the same time as the polysilicon layer formed on the gates 46 and 48, and no special process is required.
また、ポリシリコン層４４は酸化膜２６を構成
する酸化シリコン（SiO2）膜より弾力性に富み、
導電性ワイヤ６６のボンデイング時、その衝撃か
ら酸化膜２９を保護する緩衝体として機能し、酸
化膜２６のクラツキングなどの破損を防止でき
る。 Further, the polysilicon layer 44 has higher elasticity than the silicon oxide (SiO 2 ) film that constitutes the oxide film 26,
When bonding the conductive wire 66, it functions as a buffer to protect the oxide film 29 from the impact, and can prevent damage such as cracking of the oxide film 26.
しかも、このようなポリシリコン層４４が設置
された場合、接続部５６−ポリシリコン層４４−
酸化膜２６の層構造となり、ポリシリコン層４４
を設置しないで接続部５６−酸化膜２６を接合し
た場合に比較してそれぞれの密着性を高めること
ができるので、接続部５６を強固に設置すること
ができる。特に、接続部５６がアルミニウム、酸
化膜２６が酸化シリコン膜である場合、アルミニ
ウムとポリシリコンとの接合はアロイ構造とな
り、その密着性が高く、ポリシリコンと酸化シリ
コンは同種のものであり、その密着性は高くな
る。 Moreover, when such a polysilicon layer 44 is installed, the connecting portion 56 - polysilicon layer 44 -
It has a layered structure of oxide film 26, and polysilicon layer 44
Since the adhesion between the connecting portion 56 and the oxide film 26 can be improved compared to the case where the connecting portion 56 and the oxide film 26 are bonded together without installing the bonding portion 56, the connecting portion 56 can be firmly installed. In particular, when the connecting portion 56 is aluminum and the oxide film 26 is a silicon oxide film, the bond between aluminum and polysilicon has an alloy structure, and its adhesion is high. Adhesion becomes higher.
以上説明したように、この発明によれば、次の
ような効果が得られる。
As explained above, according to the present invention, the following effects can be obtained.
(a) ボンデイング用接続部と半導体基板間にポリ
シリコン層を設置して高抵抗体を挿入したの
で、ボンデイング用接続部と半導体基板間に存
在する寄生容量にポリシリコン層からなる高抵
抗体が直列に接続され、ボンデイング用接続部
と半導体基板間が高抵抗体によつて高インピー
ダンス化されて寄生容量の影響を低減でき、そ
の低減で高周波特性を著しく改善することがで
きる。(a) Since a polysilicon layer is placed between the bonding connection and the semiconductor substrate and a high resistance object is inserted, the high resistance object made of the polysilicon layer is added to the parasitic capacitance that exists between the bonding connection and the semiconductor substrate. They are connected in series, and the impedance between the bonding connection part and the semiconductor substrate is made high by a high resistance element, so that the influence of parasitic capacitance can be reduced, and the reduction can significantly improve high frequency characteristics.
(b) ポリシリコン層は、緩衝体として機能するの
で、ワイヤボンデイングの衝撃による酸化膜の
破損を防止でき、ボンデイング用接続部と半導
体基板間の短絡などの不都合を確実に防止でき
る。(b) Since the polysilicon layer functions as a buffer, it can prevent damage to the oxide film due to the impact of wire bonding, and can reliably prevent problems such as short circuits between the bonding connection and the semiconductor substrate.
(c) ボンデイング用接続部と酸化膜との間にポリ
シリコン層を介在させたことにより、ボンデイ
ング用接続部と酸化膜との間の結合強度を高め
ることができる。(c) By interposing the polysilicon layer between the bonding connection part and the oxide film, the bonding strength between the bonding connection part and the oxide film can be increased.
第１図はこの発明の半導体集積回路装置の実施
例を示す断面図、第２図は多結晶絶縁層の機能を
示す説明図、第３図は従来の半導体集積回路装置
におけるボンデイングパツド部を示す平面図、第
４図は第３図の−線に沿う断面図である。
２０……半導体基板、２４……半導体領域、２
６……酸化膜、２８……Ｎチヤンネルトランジス
タ、３０……Ｐチヤンネルトランジスタ、４４…
…多結晶絶縁層としてのポリシリコン層、５６…
…ボンデイング用接続部、６０……絶縁層、６６
……導電性ワイヤ。
FIG. 1 is a cross-sectional view showing an embodiment of a semiconductor integrated circuit device of the present invention, FIG. 2 is an explanatory diagram showing the function of a polycrystalline insulating layer, and FIG. 3 is a diagram showing a bonding pad portion in a conventional semiconductor integrated circuit device. The plan view shown in FIG. 4 is a sectional view taken along the - line in FIG. 3. 20...Semiconductor substrate, 24...Semiconductor region, 2
6...Oxide film, 28...N channel transistor, 30...P channel transistor, 44...
...Polysilicon layer as polycrystalline insulating layer, 56...
... Connection part for bonding, 60 ... Insulating layer, 66
...Conductive wire.
Claims (1)
スタ及びＰチヤンネルトランジスタを形成した半
導体集積回路装置において、 前記Ｎチヤンネルトランジスタ及びＰチヤンネ
ルトランジスタに隣接し、これらトランジスタの
形成域より僅かに窪ませた前記半導体基板の表面
層に設置され、前記半導体基板と反対導電形を成
す半導体領域と、 この半導体領域を覆つて設置されて前記半導体
基板の表面を被覆する酸化膜と、 この酸化膜の表面に選択的に形成されたポリシ
リコン層と、 前記Ｎチヤンネルトランジスタ及びＰチヤンネ
ルトランジスタの各ゲートに接続されているとと
もに、前記ポリシリコン層の上面に設置された配
線導体から成るボンデイング用接続部と、 このボンデイング用接続部に接続された導電性
ワイヤと、 前記ボンデイング用接続部を覆う絶縁層と、 を備え、前記半導体領域と前記ポリシリコン層と
の間に前記酸化膜を挟んで形成された静電容量
と、前記半導体基板と前記半導体領域との接合で
形成された接合容量と前記ポリシリコン層による
高抵抗とからなるインピーダンス回路を前記ボン
デイング用接続部と前記半導体領域との間に介在
させてなることを特徴とする半導体集積回路装
置。[Scope of Claims] 1. In a semiconductor integrated circuit device in which an N-channel transistor and a P-channel transistor are formed in a surface layer of a semiconductor substrate, a semiconductor integrated circuit device that is adjacent to the N-channel transistor and P-channel transistor and slightly recessed from the formation area of these transistors. a semiconductor region disposed on a surface layer of the semiconductor substrate and having a conductivity type opposite to that of the semiconductor substrate; an oxide film disposed to cover the semiconductor region and covering the surface of the semiconductor substrate; a polysilicon layer selectively formed on the surface; and a bonding connection portion comprising a wiring conductor connected to each gate of the N-channel transistor and the P-channel transistor and placed on the top surface of the polysilicon layer; , a conductive wire connected to the bonding connection part, and an insulating layer covering the bonding connection part, the oxide film being sandwiched between the semiconductor region and the polysilicon layer. An impedance circuit including a capacitance, a junction capacitance formed by a junction between the semiconductor substrate and the semiconductor region, and a high resistance due to the polysilicon layer is interposed between the bonding connection part and the semiconductor region. A semiconductor integrated circuit device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59125763A JPS614265A (en) | 1984-06-19 | 1984-06-19 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59125763A JPS614265A (en) | 1984-06-19 | 1984-06-19 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS614265A JPS614265A (en) | 1986-01-10 |
| JPH0345898B2 true JPH0345898B2 (en) | 1991-07-12 |
Family
ID=14918216
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59125763A Granted JPS614265A (en) | 1984-06-19 | 1984-06-19 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS614265A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56161923A (en) * | 1980-05-06 | 1981-12-12 | Ushio Electric Inc | Sterilizer for film |
| JP2008168518A (en) * | 2007-01-12 | 2008-07-24 | Advanced Telecommunication Research Institute International | Reminder apparatus |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5039470A (en) * | 1973-08-09 | 1975-04-11 | ||
| JPS5239378A (en) * | 1975-09-23 | 1977-03-26 | Seiko Epson Corp | Silicon-gated mos type semiconductor device |
-
1984
- 1984-06-19 JP JP59125763A patent/JPS614265A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5039470A (en) * | 1973-08-09 | 1975-04-11 | ||
| JPS5239378A (en) * | 1975-09-23 | 1977-03-26 | Seiko Epson Corp | Silicon-gated mos type semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS614265A (en) | 1986-01-10 |
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| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |