JP2502702B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2502702B2 JP2502702B2 JP63220976A JP22097688A JP2502702B2 JP 2502702 B2 JP2502702 B2 JP 2502702B2 JP 63220976 A JP63220976 A JP 63220976A JP 22097688 A JP22097688 A JP 22097688A JP 2502702 B2 JP2502702 B2 JP 2502702B2
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- bonding pad
- metal bonding
- insulating film
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
Description
【発明の詳細な説明】 産業上の利用分野 本発明は金属ボンディングパッドを有する半導体装置
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a metal bonding pad.
従来の技術 従来の半導体装置入出力部である金属ボンディングパ
ッドの周辺は、内部回路への配線を除いて保護膜と周囲
を接していた。2. Description of the Related Art The periphery of a metal bonding pad, which is a conventional semiconductor device input / output unit, is in contact with the periphery of a protective film except for wiring to an internal circuit.
第２図（ａ）は、従来の半導体装置の入出力部分であ
る金属ボンディングパッドの上面図である。第２図
（ｂ）は、Ａ−Ａ′断面図である。すなわち、１はたと
えばＮ型のシリコン基板、２は厚い絶縁膜、３は内部回
路へつづく多結晶シリコン配線、４は層間絶縁膜、５は
金属ボンディングパッド、６は外部接続用ピンと半導体
内部回路を接続する金属線、７は保護膜、８は金属膜と
多結晶シリコン配線を接続させるためのコンタクト窓で
ある。熱衝撃等により、半導体装置表面の保護膜７に応
力が生じたとすると、金属ボンディングパッドの側面
は、その応力を強く受ける事となり、変形し、破損する
事となる。FIG. 2A is a top view of a metal bonding pad which is an input / output portion of a conventional semiconductor device. FIG. 2B is a sectional view taken along the line AA '. That is, 1 is, for example, an N-type silicon substrate, 2 is a thick insulating film, 3 is a polycrystalline silicon wiring leading to an internal circuit, 4 is an interlayer insulating film, 5 is a metal bonding pad, 6 is an external connection pin and a semiconductor internal circuit. Metal wires to be connected, 7 is a protective film, and 8 is a contact window for connecting the metal film and the polycrystalline silicon wiring. If a stress is generated in the protective film 7 on the surface of the semiconductor device due to a thermal shock or the like, the side surface of the metal bonding pad is strongly subjected to the stress and is deformed and damaged.
発明が解決しようとする課題 このような従来の構造では、熱衝撃等で半導体装置表
面の保護膜７に応力が生じた際、金属ボンディングパッ
ド５が変形、破損するという問題点を有していた。本発
明は上記問題点に鑑み、金属ボンディングパッド５の変
形、破損を防止する事ができる半導体装置を提供するこ
とを目的とする。Problems to be Solved by the Invention Such a conventional structure has a problem that the metal bonding pad 5 is deformed or damaged when stress is generated in the protective film 7 on the surface of the semiconductor device due to thermal shock or the like. . In view of the above problems, it is an object of the present invention to provide a semiconductor device capable of preventing deformation and damage of the metal bonding pad 5.
課題を解決するための手段 この問題を解決するために、本発明は、半導体基板上
の絶縁膜面に、環状の多結晶シリコン層と，前記多結晶
シリコン層および前記絶縁膜を被う層間絶縁膜と，前記
層間絶縁膜上の前記多結晶シリコン層の環の内側に内部
回路接続のための金属ボンディングパッドと，前記多結
晶シリコン層および前記金属ボンディングパッドの周縁
部を被う保護膜とをそなえた構成である。Means for Solving the Problems In order to solve this problem, the present invention provides an annular polycrystalline silicon layer on a surface of an insulating film on a semiconductor substrate and an interlayer insulating film covering the polycrystalline silicon layer and the insulating film. A film, a metal bonding pad for connecting an internal circuit inside the ring of the polycrystalline silicon layer on the interlayer insulating film, and a protective film covering a peripheral portion of the polycrystalline silicon layer and the metal bonding pad. This is the configuration provided.
作用 上記の構成により、半導体装置表面の保護膜に応力が
生じても、その応力は、直接金属ボンディングパッドの
側面に作用せず、多結晶シリコン層によって大部分吸収
されることとなる。その結果、金属ボンディングパッド
の変形および破損を防止することが可能である。Action With the above configuration, even if a stress is generated in the protective film on the surface of the semiconductor device, the stress does not directly act on the side surface of the metal bonding pad, but is mostly absorbed by the polycrystalline silicon layer. As a result, it is possible to prevent deformation and damage of the metal bonding pad.
実施例 以下、本発明の一実施例について、図面を参照しなが
ら説明する。Embodiment One embodiment of the present invention will be described below with reference to the drawings.
第１図は本発明を示したものである。第１図（ａ）は
上面図、第１図（ｂ）は、Ｂ−Ｂ′断面図である。11は
たとえばＮ型のシリコン基板、12は厚い絶縁膜、13は内
部回路へつづく多結晶シリコン配線、14は層間絶縁膜、
15は金属ボンディングパッド、16は外部接続用ピンと半
導体内部回路を接続する金属線、17は保護膜、18は金属
膜と多結晶シリコン配線を接続するためのコンタクト
窓、19は金属ボンディングパッド15の周辺に包囲して形
成された多結晶シリコン層で、前記多結晶シリコン配線
13と同時に形成される。FIG. 1 shows the present invention. FIG. 1 (a) is a top view and FIG. 1 (b) is a BB 'sectional view. 11 is, for example, an N-type silicon substrate, 12 is a thick insulating film, 13 is polycrystalline silicon wiring leading to an internal circuit, 14 is an interlayer insulating film,
Reference numeral 15 is a metal bonding pad, 16 is a metal wire connecting the external connection pin and the semiconductor internal circuit, 17 is a protective film, 18 is a contact window for connecting the metal film and polycrystalline silicon wiring, and 19 is a metal bonding pad 15. The polycrystalline silicon layer is formed around the periphery of the polycrystalline silicon wiring.
It is formed at the same time as 13.
さて、保護膜17に応力が生じたとしても、それらの大
部分は金属ボンディングパッド15の側面には作用せず、
周囲に形成された多結晶シリコン層19により吸収され、
金属ボンディングパッド15の変形および破損を防ぐこと
ができる。Now, even if stress is generated in the protective film 17, most of them do not act on the side surface of the metal bonding pad 15,
Absorbed by the polycrystalline silicon layer 19 formed around,
It is possible to prevent deformation and damage of the metal bonding pad 15.
本発明はＮ型シリコン基板の場合を例にとったがＰ型
シリコン基板および相補型MOS電界効果トランジスタの
場合にも適用できる。Although the present invention has been described by taking the case of the N-type silicon substrate as an example, it can be applied to the case of the P-type silicon substrate and the complementary MOS field effect transistor.
発明の効果 以上説明してきた様に、本発明の半導体装置は表面の
保護膜の応力を金属ボンディングパッドの周辺に包囲し
て形成された多結晶シリコン層により吸収し、前記ボン
ディングパッドの変形、および破損を防止し、かつ信頼
性および品質を向上させる効果がある。As described above, in the semiconductor device of the present invention, the stress of the protective film on the surface is absorbed by the polycrystalline silicon layer formed surrounding the metal bonding pad, the deformation of the bonding pad, and It is effective in preventing damage and improving reliability and quality.
第１図（ａ）は本発明の実施例半導体装置の上面図、同
図（ｂ）はＢ−Ｂ′断面図、第２図（ａ）は従来の半導
体装置の上面図、同図（ｂ）は、Ａ−Ａ′断面図であ
る。 11……Ｎ型シリコン基板、12……絶縁膜、13……内部回
路へつづく多結晶シリコン配線、14……層間絶縁膜、15
……金属ボンディングパッド、16……金属線、17……保
護膜、18……金属膜と多結晶シリコン配線を接続するた
めのコンタクト窓、19……多結晶シリコン層。1A is a top view of a semiconductor device according to an embodiment of the present invention, FIG. 1B is a sectional view taken along line BB ′, and FIG. 2A is a top view of a conventional semiconductor device, FIG. ) Is a sectional view taken along line AA ′. 11 …… N-type silicon substrate, 12 …… Insulating film, 13 …… Polycrystalline silicon wiring leading to internal circuits, 14 …… Interlayer insulating film, 15
…… Metal bonding pad, 16 …… Metal wire, 17 …… Protective film, 18 …… Contact window for connecting metal film and polycrystalline silicon wiring, 19 …… Polycrystalline silicon layer.
Claims (1)
シリコン層と，前記多結晶シリコン層および前記絶縁膜
を被う層間絶縁膜と，前記層間絶縁膜上の前記多結晶シ
リコン層の環の内側に内部回路接続のための金属ボンデ
ィングパッドと，前記多結晶シリコン層および前記金属
ボンディングパッドの周縁部を被う保護膜とをそなえた
ことを特徴とする半導体装置。1. An annular polycrystalline silicon layer on an insulating film surface of a semiconductor substrate, an interlayer insulating film covering the polycrystalline silicon layer and the insulating film, and the polycrystalline silicon layer on the interlayer insulating film. A semiconductor device having a metal bonding pad for connecting an internal circuit and a protective film covering a peripheral portion of the polycrystalline silicon layer and the metal bonding pad inside the ring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63220976A JP2502702B2 (en) | 1988-09-02 | 1988-09-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63220976A JP2502702B2 (en) | 1988-09-02 | 1988-09-02 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0268943A JPH0268943A (en) | 1990-03-08 |
| JP2502702B2 true JP2502702B2 (en) | 1996-05-29 |
Family
ID=16759518
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63220976A Expired - Lifetime JP2502702B2 (en) | 1988-09-02 | 1988-09-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2502702B2 (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS617638A (en) * | 1984-06-22 | 1986-01-14 | Nec Ic Microcomput Syst Ltd | Semiconductor device |
| JPH0217842U (en) * | 1988-07-18 | 1990-02-06 |
-
1988
- 1988-09-02 JP JP63220976A patent/JP2502702B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0268943A (en) | 1990-03-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5288661A (en) | Semiconductor device having bonding pad comprising buffer layer | |
| JPH11307724A (en) | Semiconductor integrated circuit | |
| JP2502702B2 (en) | Semiconductor device | |
| JP2749241B2 (en) | Semiconductor integrated circuit | |
| JPH0268944A (en) | Semiconductor device | |
| EP0405501B1 (en) | Semiconductor device | |
| KR940012583A (en) | Semiconductor integrated circuit device and manufacturing method thereof | |
| JPH08204066A (en) | Semiconductor device | |
| JP3098333B2 (en) | Semiconductor device | |
| JP3413653B2 (en) | Semiconductor device | |
| JP2806538B2 (en) | Integrated circuit device | |
| JPS62232147A (en) | Semiconductor device | |
| JPH05275501A (en) | Semiconductor device | |
| JP2826432B2 (en) | Semiconductor device | |
| JPH01128465A (en) | Semiconductor device with antistatic element | |
| JP2680869B2 (en) | Semiconductor device | |
| JPS5827334A (en) | Semiconductor device | |
| JPH01214126A (en) | Semiconductor device | |
| JPH0511661B2 (en) | ||
| JPH01255235A (en) | Semiconductor device | |
| JPS6119163A (en) | Semiconductor integrated circuit | |
| JP2730174B2 (en) | Input protection device | |
| JPH0345898B2 (en) | ||
| JPH0274040A (en) | Semiconductor device | |
| JPH05211253A (en) | Resin sealed type semiconductor type |