JPH11307724A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPH11307724A
JPH11307724A JP11048998A JP11048998A JPH11307724A JP H11307724 A JPH11307724 A JP H11307724A JP 11048998 A JP11048998 A JP 11048998A JP 11048998 A JP11048998 A JP 11048998A JP H11307724 A JPH11307724 A JP H11307724A
Authority
JP
Japan
Prior art keywords
wiring
wiring layer
integrated circuit
semiconductor integrated
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11048998A
Other languages
Japanese (ja)
Other versions
JP3948822B2 (en
Inventor
Yasuhisa Omachi
靖久 大間知
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP11048998A priority Critical patent/JP3948822B2/en
Publication of JPH11307724A publication Critical patent/JPH11307724A/en
Application granted granted Critical
Publication of JP3948822B2 publication Critical patent/JP3948822B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

PROBLEM TO BE SOLVED: To reduce the chip size, without varying the protective element characteristics. SOLUTION: This semiconductor integrated circuit is such that protective elements, constituting an input protective circuit are disposed below bonding pads 40a, hence the size of an input part 12 is reduced by the area of the protective elements overlapped with the bonding pads 40a. On the occasion of wire bonding, the shock reaches the bonding pads 40a from a capillary but is absorbed by wiring layers 40, 38, 36 and hence excessive shock will not reach the protective elements below a wiring layer 36.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】この発明は半導体集積回路に関
し、特にたとえば基板上にそれぞれ層間絶縁層を介して
３層以上の配線層を形成した、半導体集積回路に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having, for example, three or more wiring layers formed on a substrate via an interlayer insulating layer.

【０００２】[0002]

【従来の技術】図５に示すこの種の従来の半導体集積回
路１では、内部回路の周辺部に入力部２が設けられ、こ
の入力部２にボンディングパッド３と入力保護回路４と
が平面的に配置される。入力保護回路４は、図６の等価
回路図に示すように、保護ダイオード５ａおよび５ｂな
らびに保護抵抗６ａおよび６ｂによって構成され、保護
抵抗６ａにボンディングパッド３が接続され、保護抵抗
６ｂに図示しない内部回路が接続される。そして、ボン
ディングパッド３に図示しない外部素子から所定値以上
のサージ電流が供給された場合、このサージ電流が保護
ダイオード５ａまたは５ｂのいずれかを通して設置電位
（Ｖｇｎｄ）または電源電位（Ｖｃｃ）に解放され、そ
れによって、内部回路が保護される。2. Description of the Related Art In a conventional semiconductor integrated circuit 1 of this kind shown in FIG. 5, an input section 2 is provided around an internal circuit, and a bonding pad 3 and an input protection circuit 4 are formed on the input section 2 in a planar manner. Placed in As shown in the equivalent circuit diagram of FIG. 6, the input protection circuit 4 includes protection diodes 5a and 5b and protection resistors 6a and 6b. The bonding pad 3 is connected to the protection resistor 6a. The circuit is connected. When a surge current of a predetermined value or more is supplied to the bonding pad 3 from an external element (not shown), the surge current is released to the installation potential (Vgnd) or the power supply potential (Vcc) through one of the protection diodes 5a or 5b. , Thereby protecting the internal circuit.

【０００３】[0003]

【発明が解決しようとする課題】従来技術では、ボンデ
ィングパッド３と入力保護回路４とが平面的に配置され
ていたので、これらの占める面積によって入力部２のサ
イズが決定されていた。また、サージ電流を十分に吸収
するためには、入力保護回路４を構成する各保護素子の
面積を所定の大きさ以上に確保しなければならなかっ
た。したがって、内部回路の微細化が進んでも入力部２
のサイズを縮小することはできず、チップを小型化する
ことができなかった。In the prior art, since the bonding pad 3 and the input protection circuit 4 are arranged in a plane, the size of the input section 2 is determined by the area occupied by them. In addition, in order to sufficiently absorb the surge current, the area of each protection element constituting the input protection circuit 4 must be secured to a predetermined size or more. Therefore, even if the internal circuit is miniaturized, the input unit 2
Cannot be reduced in size, and the chip cannot be miniaturized.

【０００４】なお、入力保護回路４をボンディングパッ
ド３の下方に重ねて配置すれば、入力部２の横方向への
広がりを抑えることができるが、この場合には、ワイヤ
ボンディングの際にキャピラリから受ける衝撃がボンデ
ィングパッド３下方の入力保護回路４にまで伝わるた
め、この衝撃によって各保護素子の電気的特性が変動し
てしまう恐れがあった。したがって、従来技術ではこの
構成を採用することはできなかった。If the input protection circuit 4 is disposed below the bonding pad 3 so as to overlap, the input portion 2 can be prevented from spreading in the horizontal direction. Since the received shock is transmitted to the input protection circuit 4 below the bonding pad 3, the shock may change the electrical characteristics of each protection element. Therefore, this configuration could not be adopted in the prior art.

【０００５】それゆえに、この発明の主たる目的は、保
護素子の特性変動を生じることなくチップを小型化でき
る、半導体集積回路を提供することである。[0005] Therefore, a main object of the present invention is to provide a semiconductor integrated circuit that can reduce the size of a chip without causing a change in the characteristics of a protection element.

【０００６】[0006]

【課題を解決するための手段】この発明は、基板上にそ
れぞれ層間絶縁層を介して３層以上の配線層を形成した
半導体集積回路において、基板に保護回路を構成する保
護素子を形成し、保護素子と最下配線層とをプラグを介
して接続し、最上配線層にボンディングパッドを形成
し、最下配線層と最上配線層とを中間配線層を介して接
続したことを特徴とする、半導体集積回路である。According to the present invention, in a semiconductor integrated circuit having three or more wiring layers formed on a substrate with an interlayer insulating layer interposed therebetween, a protection element constituting a protection circuit is formed on the substrate. Connecting the protection element and the lowermost wiring layer via a plug, forming a bonding pad on the uppermost wiring layer, and connecting the lowermost wiring layer and the uppermost wiring layer via an intermediate wiring layer, It is a semiconductor integrated circuit.

【０００７】[0007]

【作用】保護回路を構成する保護素子がボンディングパ
ッドの下方に配置されるので、保護素子とボンディング
パッドとが重なる部分の面積だけ、入力部または出力部
のサイズが縮小される。ワイヤボンディングの際には、
ボンディングワイヤを押圧するためのキャピラリからボ
ンディングパッドへ衝撃が伝わるが、３層以上の各配線
層がこの衝撃を吸収するので、下層へ向かうほど衝撃が
緩和される。したがって、最下配線層のさらに下方に配
置された保護素子に過大な衝撃が伝わることはない。Since the protection element constituting the protection circuit is arranged below the bonding pad, the size of the input section or the output section is reduced by the area of the portion where the protection element and the bonding pad overlap. In the case of wire bonding,
The shock is transmitted from the capillary for pressing the bonding wire to the bonding pad, but the three or more wiring layers absorb the shock, so that the shock is reduced toward the lower layer. Therefore, an excessive impact is not transmitted to the protection element disposed further below the lowermost wiring layer.

【０００８】[0008]

【発明の効果】この発明によれば、入力部または出力部
のサイズを縮小できるので、チップを小型化できる。し
たがって、単位面積当たりのチップの取れ数を向上で
き、チップのコストを低減できる。しかも、保護素子に
過大な衝撃が伝わるのを防止できるので、保護素子の電
気的特性が変動することもない。According to the present invention, since the size of the input section or the output section can be reduced, the chip can be downsized. Therefore, the number of chips per unit area can be increased, and the cost of the chips can be reduced. In addition, since an excessive impact can be prevented from being transmitted to the protection element, the electrical characteristics of the protection element do not change.

【０００９】この発明の上述の目的，その他の目的，特
徴および利点は、図面を参照して行う以下の実施例の詳
細な説明から一層明らかとなろう。The above objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

【００１０】[0010]

【実施例】図１〜図３に示すこの実施例の半導体集積回
路１０は、ＬＳＩ（大規模集積回路）やＶＬＳＩ（超大
規模集積回路）等に適用されるものであり、内部回路と
その周囲に配置された入力部１２とを含む。入力部１２
には、図４の等価回路図で示される入力保護回路１２ａ
が構成され、この入力保護回路１２ａによって外部素子
からのサージ電流が吸収される。DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor integrated circuit 10 of this embodiment shown in FIGS. 1 to 3 is applied to an LSI (Large Scale Integrated Circuit), a VLSI (Very Large Scale Integrated Circuit), and the like. And an input unit 12 arranged at the same time. Input unit 12
The input protection circuit 12a shown in the equivalent circuit diagram of FIG.
The surge current from an external element is absorbed by the input protection circuit 12a.

【００１１】半導体集積回路１０は、シリコン（Ｓｉ）
等からなる一導電型（Ｐ型またはＮ型）の基板１４を含
み、基板１４の上部には、Ｐ型の拡散領域からなるＰウ
ェル１６ａとＮ型の拡散領域からなるＮウェル１６ｂと
が隣接して形成され、基板１４の上面には、フィールド
酸化膜１８が形成される。そして、Ｐウェル１６ａの表
面中央部には不純物濃度の高いＮ+ 拡散領域２０ａが形
成され、Ｎウェル１６ｂの表面中央部には不純物濃度の
高いＰ+ 拡散領域２０ｂが形成され、Ｎ+ 拡散領域２０
ａとＰウェル１６ａとの間でＰ／Ｎ接合部すなわちダイ
オ−ド２２ａ（図４）が構成され、Ｐ+ 拡散領域２０ｂ
とＮウェル１６ｂとの間でダイオ−ド２２ｂ（図４）が
構成される。また、Ｎ+ 拡散領域２０ａおよびＰ+ 拡散
領域２０ｂのそれぞれから所定間隔を隔てた位置にこれ
らを個別に包囲するようにして不純物濃度の高いＰ+ コ
ンタクト領域２４ａおよびＮ+ コンタクト領域２４ｂが
形成される。また、Ｐウェル１６ａとＮウェル１６ｂと
の境界上に位置するフィ−ルド酸化膜１８の上面には、
図４に示した保護抵抗２６ａおよび２６ｂを構成するポ
リシリコン等からなる配線２８が形成され、配線２８の
一端が図示しない内部回路に接続される。The semiconductor integrated circuit 10 is made of silicon (Si)
And the like. A P-well 16a composed of a P-type diffusion region and an N-well 16b composed of an N-type diffusion region are adjacent to each other on the upper side of the substrate 14 including a substrate 14 of one conductivity type (P-type or N-type). The field oxide film 18 is formed on the upper surface of the substrate 14. The high N + diffusion region 20a of impurity concentration is formed in the center part of the surface of P-well 16a, a high P + diffusion region 20b impurity concentration is formed in the center part of the surface of N-well 16b, N + diffusion region 20
P / N junction i.e. diode between the a and P-well 16a - de 22a (FIG. 4) is configured, P + diffusion region 20b
A diode 22b (FIG. 4) is formed between the N well 16b. Further, P + contact regions 24a and N + contact regions 24b having a high impurity concentration are formed so as to individually surround the N + diffusion regions 20a and the P + diffusion regions 20b at positions separated from each other by a predetermined distance. You. Further, on the upper surface of the field oxide film 18 located on the boundary between the P well 16a and the N well 16b,
Wiring 28 made of polysilicon or the like constituting protection resistors 26a and 26b shown in FIG. 4 is formed, and one end of wiring 28 is connected to an internal circuit (not shown).

【００１２】そして、フィールド酸化膜１８上に酸化シ
リコン（ＳｉＯ2 ）等からなる層間絶縁層３０ａが形成
され、層間絶縁層３０ａにＮ+ 拡散領域２０ａ，Ｐ+ 拡
散領域２０ｂ，Ｐ+ コンタクト領域２４ａ，Ｎ+ コンタ
クト領域２４ｂおよび配線２８のそれぞれに連通するコ
ンタクトホール３２が形成され、このコンタクトホール
３２にタングステン（Ｗ）等からなるプラグ３４が埋め
込まれる。そして、層間絶縁層３０ａおよびプラグ３４
の上面にアルミニウム（Ａｌ）または銅（Ｃｕ）等の金
属からなる第１配線層３６が形成され、その上に同金属
からなる第２配線層３８および第３配線層４０が酸化シ
リコン（ＳｉＯ2 ）等からなる層間絶縁層３０ｂおよび
３０ｃを介して形成され、さらに第３配線層４０の周縁
部を覆うようにして酸化シリコン（ＳｉＯ2 ）等からな
る絶縁層４２が形成される。An interlayer insulating layer 30a made of silicon oxide (SiO 2 ) or the like is formed on the field oxide film 18, and the N + diffusion region 20a, the P + diffusion region 20b, and the P + contact region 24a are formed on the interlayer insulating layer 30a. , N + contact region 24b and interconnect 28 are formed, and plug 34 made of tungsten (W) or the like is embedded in contact hole 32. Then, the interlayer insulating layer 30a and the plug 34
A first wiring layer 36 made of a metal such as aluminum (Al) or copper (Cu) is formed on the upper surface of the substrate, and a second wiring layer 38 and a third wiring layer 40 made of the same metal are formed on the first wiring layer 36 by using silicon oxide (SiO 2). ) And the like, and an insulating layer 42 made of silicon oxide (SiO 2 ) or the like is formed so as to cover the peripheral portion of the third wiring layer 40.

【００１３】第１配線層３６は、バッファ部３６ａおよ
び配線接続部３６ｂ（図３）を含みバッファ部３６ａと
Ｎ+ 拡散領域２０ａ，Ｐ+ 拡散領域２０ｂおよび配線２
８のそれぞれとがプラグ３４を介して接続され、配線接
続部３６ｂと配線２８とがプラグ３４を介して接続され
る。第１配線層３６に接続されないＰ+ コンタクト領域
２４ａおよびＮ+ コンタクト領域２４ｂはプラグ３４を
介して図示しないＧＮＤ配線およびＶｃｃ配線に接続さ
れる。第２配線層３８は、他の素子と接続されないアイ
ランド状のバッファ部３８ａおよび配線接続部３８ｂ
（図３）を含み、配線接続部３８ｂと配線接続部３６ｂ
とが層間絶縁層３０ｂに形成されたタングステン（Ｗ）
等からなるプラグ４４を介して接続される。第３配線層
４０は、ボンディングパッド４０ａを含み、このボンデ
ィングパッド４０ａが層間絶縁層３０ｃに形成されたタ
ングステン（Ｗ）等からなるプラグ４６を介して配線接
続部３８ｂに接続される。各配線層３６，３８および４
０の面積は、入力保護回路１２ａを構成する各素子（少
なくともＮ+ 拡散領域２０ａおよびＰ+ 拡散領域２０
ｂ）を覆うことのできる大きさに設定される。なお、各
配線層３６，３８および４０のサイズや位置関係は、半
導体集積回路１０のサイズや電気的要件や設計仕様等に
基づいて決定され、たとえば、一辺のサイズが３０μｍ
〜３００μｍの範囲の矩形状で、層厚０．３μｍ〜３μ
ｍの範囲、および相互の間隔が１０μｍ〜３００μｍの
範囲で実施可能である。The first wiring layer 36 includes a buffer portion 36a and a wiring connection portion 36b (FIG. 3), and includes the buffer portion 36a, the N + diffusion region 20a, the P + diffusion region 20b, and the wiring 2
8 are connected via a plug 34, and the wiring connection portion 36 b and the wiring 28 are connected via the plug 34. The P + contact region 24a and the N + contact region 24b that are not connected to the first wiring layer 36 are connected to a GND wiring and a Vcc wiring (not shown) via the plug 34. The second wiring layer 38 includes an island-shaped buffer portion 38a and a wiring connection portion 38b that are not connected to other elements.
(FIG. 3), the wiring connecting portion 38b and the wiring connecting portion 36b
And tungsten (W) formed on the interlayer insulating layer 30b.
The connection is made via a plug 44 made of the same. The third wiring layer 40 includes a bonding pad 40a, and the bonding pad 40a is connected to the wiring connection part 38b via a plug 46 made of tungsten (W) or the like formed on the interlayer insulating layer 30c. Each wiring layer 36, 38 and 4
The area of 0 corresponds to each element constituting the input protection circuit 12a (at least the N + diffusion region 20a and the P +
b) is set to a size that can cover b). The size and positional relationship of each of the wiring layers 36, 38, and 40 are determined based on the size, electrical requirements, design specifications, and the like of the semiconductor integrated circuit 10. For example, the size of one side is 30 μm.
Rectangular shape with a thickness of 0.3 μm to 3 μm
It can be implemented in the range of m and the interval between each other in the range of 10 μm to 300 μm.

【００１４】なお、各配線層３６，３８および４０を形
成する際には、ボンディングパッド４０ａの表面を平坦
にしてボンディングの際の接合性を向上するために、層
間絶縁層３０ａ，３０ｂおよび３０ｃならびにプラグ３
４，４４および４６のそれぞれの上面がＣＭＰ（化学的
機械研磨）等のような周知の平坦化プロセスによって平
坦化される。When forming the wiring layers 36, 38 and 40, the interlayer insulating layers 30a, 30b and 30c and the interlayer insulating layers 30a, 30b and 30c are formed in order to make the surface of the bonding pad 40a flat and improve the bonding property at the time of bonding. Plug 3
The top surface of each of 4, 44 and 46 is planarized by a known planarization process such as CMP (chemical mechanical polishing) or the like.

【００１５】そして、この半導体集積回路１０を含むチ
ップがリード・フレーム上にマウンティングされ、ボン
ディングパッド４０ａとリード・フレームの対応するリ
ードとがアルミニウム（Ａｌ）または金（Ａｕ）等のボ
ンディングワイヤを用いて接続される。このボンディン
グ工程では、筒状のキャピラリに通されたボンディング
ワイヤの下端に球状のボールが形成され、そのボールが
ボンディングパッド４０ａの上面に所定のボンド荷重で
押圧されて超音波により接続される。そのため、キャピ
ラリからボンディングパッド４０ａへ過大な衝撃が加わ
るが、この衝撃は比較的軟らかいアルミニウム（Ａｌ）
または銅（Ｃｕ）等の金属からなる各配線層３０，３２
および３４によって吸収される。A chip including the semiconductor integrated circuit 10 is mounted on a lead frame, and the bonding pad 40a and a corresponding lead of the lead frame are formed using a bonding wire such as aluminum (Al) or gold (Au). Connected. In this bonding step, a spherical ball is formed at the lower end of the bonding wire passed through the cylindrical capillary, and the ball is pressed against the upper surface of the bonding pad 40a with a predetermined bonding load and connected by ultrasonic waves. For this reason, an excessive impact is applied from the capillary to the bonding pad 40a, but the impact is relatively soft aluminum (Al).
Alternatively, each of the wiring layers 30 and 32 made of a metal such as copper (Cu)
And 34.

【００１６】半導体集積回路１０を装置に組み込んだ
後、図示しない外部素子からボンディングパッド４０ａ
へ電流が供給されると、この電流は第２配線層３８の配
線接続部３８ｂ、第１配線層３６の配線接続部３６ｂお
よび抵抗２６ａおよび２６ｂ（図４）を構成する配線２
８を通して図示しない内部回路へ供給される。このと
き、供給された電流の値が所定値以下であれば、その電
流がそのまま内部回路へ供給される。一方、電流値が所
定値を超える場合には、ダイオ−ド２２ａまたは２２ｂ
のいずれかがオンされ、この電流（サージ電流）が接地
電位（Ｖｇｎｄ）または電源電位（Ｖｃｃ）に解放され
て内部回路が保護される。After assembling the semiconductor integrated circuit 10 into the device, bonding pads 40 a
When a current is supplied to the second wiring layer 38, the current is supplied to the wiring connection part 38 b of the second wiring layer 38, the wiring connection part 36 b of the first wiring layer 36, and the wirings 2 forming the resistors 26 a and 26 b (FIG. 4).
The signal is supplied to an internal circuit (not shown) through the line 8. At this time, if the value of the supplied current is equal to or less than a predetermined value, the current is directly supplied to the internal circuit. On the other hand, if the current value exceeds a predetermined value, the diode 22a or 22b
Is turned on, this current (surge current) is released to the ground potential (Vgnd) or the power supply potential (Vcc), and the internal circuit is protected.

【００１７】この実施例によれば、ワイヤボンディング
の際にキャピラリから受けた衝撃を第３配線層４０（ボ
ンディングパッド４０ａ），第２配線層３８および第１
配線層３６によって吸収できるので、入力保護回路１２
ａを構成する各素子の電気的特性が衝撃によって変動さ
れることはない。したがって、ボンディングパッド４０
ａの下方に入力保護回路１２ａを配置した構成でも何ら
問題はなく、この構成よって、入力部１２の横方向への
広がりを抑えることができ、チップを小型化できる。ま
た、単位面積当たりのチップの取れ数を向上でき、チッ
プのコストを低減できる。According to this embodiment, the impact received from the capillary during wire bonding is applied to the third wiring layer 40 (bonding pad 40a), the second wiring layer 38, and the first wiring layer 38.
Since it can be absorbed by the wiring layer 36, the input protection circuit 12
The electrical characteristics of each element constituting a are not changed by the impact. Therefore, the bonding pad 40
There is no problem with the configuration in which the input protection circuit 12a is disposed below the input terminal a. With this configuration, the input unit 12 can be prevented from spreading in the horizontal direction, and the chip can be downsized. In addition, the number of chips per unit area can be increased, and the cost of the chips can be reduced.

【００１８】また、ＣＭＰ（化学的機械研磨）等のよう
な平坦化プロセスを用いて各層を形成し、ボンディング
パッド４０ａの表面を平坦にしているので、ボンディン
グパッド４０ａに対してボンディングワイヤ（ボール）
を確実に接合できる。なお、上述の実施例では、３層配
線構造に組み込まれた入力保護回路について説明した
が、この発明は４層以上の配線構造に組み込まれた入力
保護回路や３層以上の配線構造に組み込まれた出力保護
回路についても同様に適用できる。Further, since each layer is formed by using a flattening process such as CMP (Chemical Mechanical Polishing) and the surface of the bonding pad 40a is flattened, a bonding wire (ball) is formed on the bonding pad 40a.
Can be securely joined. In the above embodiment, the input protection circuit incorporated in a three-layer wiring structure has been described. However, the present invention is incorporated in an input protection circuit incorporated in a four-layer wiring structure or a three-layer wiring structure. The same can be applied to the output protection circuit.

【図面の簡単な説明】[Brief description of the drawings]

【図１】この発明の一実施例を示す図解図である。FIG. 1 is an illustrative view showing one embodiment of the present invention;

【図２】図１におけるII−II線断面図である。FIG. 2 is a sectional view taken along line II-II in FIG.

【図３】図１におけるIII-III 線断面図である。FIG. 3 is a sectional view taken along line III-III in FIG.

【図４】図１実施例の入力保護回路を示す等価回路図で
ある。FIG. 4 is an equivalent circuit diagram showing the input protection circuit of the embodiment in FIG. 1;

【図５】従来技術を示す図解図である。FIG. 5 is an illustrative view showing a conventional technique;

【図６】従来技術の入力保護回路を示す等価回路図であ
る。FIG. 6 is an equivalent circuit diagram showing a conventional input protection circuit.

【符号の説明】[Explanation of symbols]

１０ …半導体集積回路 １２ …入力部 １２ａ …入力保護回路 １４ …基板 ２８ …配線 ３０ａ，３０ｂ，３０ｃ …層間絶縁層 ３６ …第１配線層 ３８ …第２配線層 ４０ …第３配線層 ４０ａ …ボンディングパッド DESCRIPTION OF SYMBOLS 10 ... Semiconductor integrated circuit 12 ... Input part 12a ... Input protection circuit 14 ... Substrate 28 ... Wiring 30a, 30b, 30c ... Interlayer insulating layer 36 ... First wiring layer 38 ... Second wiring layer 40 ... Third wiring layer 40a ... Bonding pad

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】基板上にそれぞれ層間絶縁層を介して３層
以上の配線層を形成した半導体集積回路において、 前記基板に保護回路を構成する保護素子を形成し、前記
保護素子と最下配線層とをプラグを介して接続し、最上
配線層にボンディングパッドを形成し、前記最下配線層
と前記最上配線層とを中間配線層を介して接続したこと
を特徴とする、半導体集積回路。1. A semiconductor integrated circuit having three or more wiring layers formed on a substrate with an interlayer insulating layer interposed therebetween, wherein a protection element forming a protection circuit is formed on the substrate, and the protection element and a lowermost wiring are formed. A semiconductor integrated circuit, wherein the layers are connected via a plug, a bonding pad is formed on an uppermost wiring layer, and the lowermost wiring layer and the uppermost wiring layer are connected via an intermediate wiring layer. 【請求項２】前記配線層は金属層を含む、請求項１記載
の半導体集積回路。2. The semiconductor integrated circuit according to claim 1, wherein said wiring layer includes a metal layer. 【請求項３】前記配線層は平坦化された前記層間絶縁層
の上面に形成される、請求項１または２記載の半導体集
積回路。3. The semiconductor integrated circuit according to claim 1, wherein said wiring layer is formed on an upper surface of said planarized interlayer insulating layer.
JP11048998A 1998-04-21 1998-04-21 Semiconductor integrated circuit Expired - Fee Related JP3948822B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11048998A JP3948822B2 (en) 1998-04-21 1998-04-21 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11048998A JP3948822B2 (en) 1998-04-21 1998-04-21 Semiconductor integrated circuit

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Publication Number Publication Date
JPH11307724A true JPH11307724A (en) 1999-11-05
JP3948822B2 JP3948822B2 (en) 2007-07-25

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