JP2008066760A - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
JP2008066760A
JP2008066760A JP2007305584A JP2007305584A JP2008066760A JP 2008066760 A JP2008066760 A JP 2008066760A JP 2007305584 A JP2007305584 A JP 2007305584A JP 2007305584 A JP2007305584 A JP 2007305584A JP 2008066760 A JP2008066760 A JP 2008066760A
Authority
JP
Japan
Prior art keywords
wiring
buffer layer
pad
semiconductor device
connecting portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2007305584A
Other languages
Japanese (ja)
Other versions
JP2008066760A5 (en
JP4835873B2 (en
Inventor
Takeshi Yuzawa
健 湯澤
Masatoshi Tagaki
昌利 田垣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP2007305584A priority Critical patent/JP4835873B2/en
Publication of JP2008066760A publication Critical patent/JP2008066760A/en
Publication of JP2008066760A5 publication Critical patent/JP2008066760A5/ja
Application granted granted Critical
Publication of JP4835873B2 publication Critical patent/JP4835873B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

<P>PROBLEM TO BE SOLVED: To reduce stress developed in wiring joints of different widths. <P>SOLUTION: A semiconductor device includes a semiconductor chip 10, the joint 34 to connect a first and a second wiring having different width, a pad 40 formed in a position overlapping the joint 34, a bump 44 formed on the pad 40, a buffer layer 50 positioned between the joint 34 and the pad 40 and formed like covering the whole joint 34, and inorganic insulating layers 60, 62 formed between the joint 34 and the buffer layer 50, and between the buffer layer 50 and the pad 40, respectively. The buffer layer 50 is formed of a material excluding resin and softer than the inorganic insulating layers 60, 62. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、半導体装置に関する。   The present invention relates to a semiconductor device.

集積回路チップとしての半導体チップには、多層の配線が形成されている。いくつかの配線は、幅の広い部分と狭い部分を有するが、このような幅の異なる部分の連結部分には、応力が集中し易くなる。特に最下層に形成されるゲート電極から引き出されるポリシリコン配線は金属と比べ、延性に劣るため、連結部分でのクラックが生じやすく、断線を引き起こすという問題があった。同じポリシリコンで形成される抵抗素子も同様の問題があった。
特開２００２−３１９５８７号公報 A multi-layer wiring is formed on a semiconductor chip as an integrated circuit chip. Some wirings have a wide part and a narrow part, but stress tends to concentrate on the connecting part of such different parts. In particular, the polysilicon wiring led out from the gate electrode formed in the lowermost layer is inferior in ductility as compared with metal, so that there is a problem that cracks are likely to occur at the connecting portion, causing disconnection. Resistance elements formed of the same polysilicon have the same problem.
JP 2002-319587 A

本発明の目的は、配線または抵抗素子の、幅の異なる部分の連結部分に生じる応力を減らすことにある。   An object of the present invention is to reduce a stress generated in a connection portion of portions having different widths of a wiring or a resistance element.

（１）本発明に係る半導体装置は、
半導体チップと、
前記半導体チップに作り込まれてなる、幅の異なる部分の連結部分を有する配線と、
前記配線の上方であって、前記連結部分とオーバーラップする位置に形成されたパッドと、
前記パッド上に形成されてなるバンプと、
前記連結部分と前記パッドとの間に位置して前記連結部分の全体を覆うように形成されてなる緩衝層と、
前記配線と前記緩衝層との間及び前記緩衝層と前記パッドとの間に、それぞれ形成されてなる無機絶縁層と、
を含み、
前記緩衝層は、樹脂を除く材料であって、前記無機絶縁層よりも柔らかい材料から形成されてなる。本発明によれば、幅の異なる部分の連結部分に対してバンプから力が加えられても、緩衝層によって力が吸収されるので、連結部分に生じる応力を減らすことができる。
（２）この半導体装置において、
前記配線は抵抗素子として用いられてもよい。
（３）この半導体装置において、
前記緩衝層は、導電材料から形成され、前記配線に電気的に接続されていてもよい。
（４）この半導体装置において、
前記配線はポリシリコンによって形成されてもよい。 (1) A semiconductor device according to the present invention includes:
A semiconductor chip;
A wiring formed in the semiconductor chip and having a connecting portion of different widths;
A pad formed above the wiring and at a position overlapping the connecting portion;
A bump formed on the pad;
A buffer layer formed between the connecting portion and the pad so as to cover the entire connecting portion;
An inorganic insulating layer formed between the wiring and the buffer layer and between the buffer layer and the pad;
Including
The buffer layer is made of a material excluding resin and softer than the inorganic insulating layer. According to the present invention, even if force is applied from the bumps to the connecting portions having different widths, the force is absorbed by the buffer layer, so that the stress generated in the connecting portions can be reduced.
(2) In this semiconductor device,
The wiring may be used as a resistance element.
(3) In this semiconductor device,
The buffer layer may be formed of a conductive material and electrically connected to the wiring.
(4) In this semiconductor device,
The wiring may be formed of polysilicon.

以下、本発明の実施の形態について図面を参照して説明する。   Embodiments of the present invention will be described below with reference to the drawings.

（第１の実施の形態）
図１（Ａ）は、本発明の第１の実施の形態に係る半導体装置の一部を示す断面図である。図１（Ｂ）は、図１（Ａ）に示す半導体装置の一部を示す平面図である。半導体装置は、半導体チップ１０を有する。半導体チップ１０には、集積回路（例えば電界効果トランジスタ２０）が作り込まれている。 (First embodiment)
FIG. 1A is a cross-sectional view showing a part of the semiconductor device according to the first embodiment of the present invention. FIG. 1B is a plan view illustrating a part of the semiconductor device illustrated in FIG. The semiconductor device has a semiconductor chip 10. An integrated circuit (for example, a field effect transistor 20) is built in the semiconductor chip 10.

電界効果トランジスタ２０は、ソース及びドレインとなる拡散層２１，２２と、拡散層２１，２２とのコンタクト部２３，２４と、ゲート電極２５と、を有する。ゲート電極２５に電圧を加えるとチャネル２６が形成されて電流が流れる。   The field effect transistor 20 includes diffusion layers 21 and 22 serving as a source and a drain, contact portions 23 and 24 with the diffusion layers 21 and 22, and a gate electrode 25. When a voltage is applied to the gate electrode 25, a channel 26 is formed and a current flows.

半導体チップ１０には、配線３０が作り込まれている。配線３０は、コンタクト部２３、２４を介して、ソース及びドレイン領域となっている拡散層２１、２２と接続されている。   A wiring 30 is formed in the semiconductor chip 10. The wiring 30 is connected to the diffusion layers 21 and 22 serving as the source and drain regions via the contact portions 23 and 24.

半導体チップ１０には、ゲート電極２５と接続され、第１の幅を有する第１の配線２５ａと、第２の幅を有する第２の配線２５ｂと、第１の配線２５ａと第２の配線２５ｂの連結部分３４と、を有する。第１の幅は第２の幅よりも狭い。第１の配線２５ａ及び第２の配線２５ｂ、連結部分３４とで、図１（Ｂ）のように、Ｔ字状となっていてもよいし、変形例として、図２（Ａ）のようにＬ字状であってもよいし、図２（Ｂ）のように十字状であってもよい。第１の配線２５ａと第２の配線２５ｂを、ポリシリコン、アルミニウム（Ａｌ）、アルミニウム合金等から形成してもよい。第１の配線２５ａと第２の配線２５ｂを、ポリシリコンから形成し、これらを抵抗素子として用いてもよい。幅の異なる第１の配線２５ａと第２の配線２５ｂに力が加えられると、連結部分３４に応力が集中することが知られている。   The semiconductor chip 10 is connected to the gate electrode 25 and has a first wiring 25a having a first width, a second wiring 25b having a second width, a first wiring 25a, and a second wiring 25b. Connecting portion 34. The first width is narrower than the second width. The first wiring 25a, the second wiring 25b, and the connecting portion 34 may be T-shaped as shown in FIG. 1B, or as a modification, as shown in FIG. 2A. It may be L-shaped or cross-shaped as shown in FIG. The first wiring 25a and the second wiring 25b may be formed of polysilicon, aluminum (Al), aluminum alloy, or the like. The first wiring 25a and the second wiring 25b may be formed from polysilicon and used as resistance elements. It is known that when force is applied to the first wiring 25a and the second wiring 25b having different widths, stress is concentrated on the connecting portion 34.

連結部分３４とオーバーラップする位置（連結部分３４の上方）にはパッド４０が配置されている。パッド４０は、集積回路に電気的に接続される。パッド４０は、ＴｉＮ又はＴｉＷ等からなるバリアメタル層を最上層に含んでもよい。バリアメタル層は、その上に形成される部材の材料がパッド４０内に拡散することを防止することができる。パッド４０は、スパッタリングによって形成することができる。   A pad 40 is disposed at a position overlapping the connecting portion 34 (above the connecting portion 34). The pad 40 is electrically connected to the integrated circuit. The pad 40 may include a barrier metal layer made of TiN or TiW as the uppermost layer. The barrier metal layer can prevent the material of the member formed thereon from diffusing into the pad 40. The pad 40 can be formed by sputtering.

パッド４０を一部として含む配線は、パッド４０の少なくとも一部（例えば中央部）を除いて、パッシベーション膜４２に覆われている。パッシベーション膜４２は、ＳｉＯ2、ＳｉＮなどの無機材料から形成されている。無機材料は、Ａｕ、Ａｌなどの金属よりも硬いことで知られている。 The wiring including the pad 40 as a part is covered with the passivation film 42 except for at least a part (for example, the central part) of the pad 40. The passivation film 42 is formed from an inorganic material such as SiO 2 or SiN. Inorganic materials are known to be harder than metals such as Au and Al.

パッド４０上にはバンプ４４が形成されている。バンプ４４は、Ａｕなどの金属から形成されている。Ａｕは、ＴｉＮ又はＴｉＷよりも柔らかい。バンプ４４は、その一部がパッシベーション膜４２上に載っていてもよい。バンプ４４は、電解メッキで形成することができる。   Bumps 44 are formed on the pad 40. The bumps 44 are formed from a metal such as Au. Au is softer than TiN or TiW. A part of the bump 44 may be placed on the passivation film 42. The bumps 44 can be formed by electrolytic plating.

連結部分３４とパッド４０との間には、緩衝層５０が配置されている。緩衝層５０は、連結部分３４の全体を覆うように形成されている。第１の配線２５ａ、第２の配線２５ｂと緩衝層５０との間及び緩衝層５０とパッド４０との間に、それぞれ、無機絶縁層６０，６２が形成されている。無機絶縁層６０，６２は、酸化膜などの無機材料から形成されており、無機材料はＡｕ、Ａｌなどの金属よりも硬いことで知られている。緩衝層５０は、樹脂を除く材料であって、無機絶縁層６０，６２よりも柔らかい材料（例えば金属）から形成されている。緩衝層５０は、配線３０及びパッド４０の少なくとも一方と同じ材料で形成してもよい。   A buffer layer 50 is disposed between the connecting portion 34 and the pad 40. The buffer layer 50 is formed so as to cover the entire connecting portion 34. Inorganic insulating layers 60 and 62 are formed between the first wiring 25a, the second wiring 25b, and the buffer layer 50, and between the buffer layer 50 and the pad 40, respectively. The inorganic insulating layers 60 and 62 are made of an inorganic material such as an oxide film, and the inorganic material is known to be harder than a metal such as Au or Al. The buffer layer 50 is a material excluding resin, and is formed of a material (for example, metal) softer than the inorganic insulating layers 60 and 62. The buffer layer 50 may be formed of the same material as at least one of the wiring 30 and the pad 40.

本実施の形態によれば、幅の異なる部分の連結部分３４に対してバンプ４４から力が加えられても、緩衝層５０によって力が吸収されるので、連結部分３４に生じる応力を減らすことができる。   According to the present embodiment, even if a force is applied from the bump 44 to the connecting portion 34 of a portion having a different width, the force is absorbed by the buffer layer 50, so that the stress generated in the connecting portion 34 can be reduced. it can.

（第２の実施の形態）
図３（Ａ）は、本発明の第２の実施の形態に係る半導体装置の一部を示す断面図である。図３（Ｂ）は、図３（Ａ）に示す半導体装置の一部を示す平面図である。なお、図３（Ａ）は、図３（Ｂ）中のIIIA−IIIA線断面図となっている。 (Second Embodiment)
FIG. 3A is a cross-sectional view showing a part of the semiconductor device according to the second embodiment of the present invention. FIG. 3B is a plan view illustrating part of the semiconductor device illustrated in FIG. Note that FIG. 3A is a cross-sectional view taken along the line IIIA-IIIA in FIG.

この例の半導体装置１１０は、第１の幅を有する第１の配線１２５ａと、第２の幅を有する第２の配線１２５ｂと、第１の配線１２５ａと第２の配線１２５ｂとの連結部分１３４とを有する。   In this example, the semiconductor device 110 includes a first wiring 125a having a first width, a second wiring 125b having a second width, and a connecting portion 134 between the first wiring 125a and the second wiring 125b. And have.

緩衝層１５０は、導電材料から形成され、第２の配線１２５ｂに電気的に接続されていている。詳しくは、緩衝層１５０と第２の配線１２５ｂの間にコンタクト部７０が設けられて電気的な接続が図られている。第２の配線１２５ｂにおいて、コンタクト部７０を設けるために、第２の配線１２５ｂの第２の幅は、第１の配線１２５ａの第１の幅よりも広くなっている。緩衝層１５０は、連結部分１３４を覆うように形成されている。また、緩衝層１５０は連結部分１３４とパッド１４０の間に形成されている。その他の構成は、上述した実施の形態で説明した内容が該当し、その作用効果についても同じである。   The buffer layer 150 is made of a conductive material and is electrically connected to the second wiring 125b. Specifically, a contact portion 70 is provided between the buffer layer 150 and the second wiring 125b to achieve electrical connection. In order to provide the contact portion 70 in the second wiring 125b, the second width of the second wiring 125b is wider than the first width of the first wiring 125a. The buffer layer 150 is formed so as to cover the coupling portion 134. The buffer layer 150 is formed between the connecting portion 134 and the pad 140. The other configurations correspond to the contents described in the above-described embodiment, and the same effects are obtained.

（第３の実施の形態）
図４（Ａ）は、本発明の第３の実施の形態に係る半導体装置の一部を示す断面図である。図４（Ｂ）は、図４（Ａ）に示す半導体装置の一部を示す平面図である。半導体装置は、半導体チップ２１０を有する。半導体チップ２１０には、集積回路（例えば電界効果トランジスタ２２０）が作り込まれている。 (Third embodiment)
FIG. 4A is a cross-sectional view showing a part of a semiconductor device according to the third embodiment of the present invention. FIG. 4B is a plan view illustrating part of the semiconductor device illustrated in FIG. The semiconductor device has a semiconductor chip 210. An integrated circuit (for example, a field effect transistor 220) is built in the semiconductor chip 210.

電界効果トランジスタ２２０は、ソース及びドレインとなる拡散層２２１，２２２と、拡散層２２１，２２２とのコンタクト部２２３，２２４と、ゲート電極２２５と、を有する。ゲート電極２２５に電圧を加えるとチャネル２２６が形成されて電流が流れる。   The field effect transistor 220 includes diffusion layers 221 and 222 serving as a source and a drain, contact portions 223 and 224 with the diffusion layers 221 and 222, and a gate electrode 225. When a voltage is applied to the gate electrode 225, a channel 226 is formed and a current flows.

半導体チップ２１０には、配線２３０が作り込まれている。配線２３０は、幅の異なる部分２３１，２３２と、これらの連結部分２３４を有する。狭い方の部分２３２は配線ラインであり、幅の広い部分２３２にコンタクト部２２３が設けられている。幅の異なる部分２３１，２３２及び連結部分２３４の形状は、Ｌ字、Ｔ字又は十字のいずれであってもよい。幅の異なる部分２３１，２３２を含む配線２３０に力が加えられると、連結部分２３４に応力が集中することが知られている。   A wiring 230 is formed in the semiconductor chip 210. The wiring 230 includes portions 231 and 232 having different widths and a connecting portion 234 thereof. The narrower portion 232 is a wiring line, and the contact portion 223 is provided in the wider portion 232. The shapes of the portions 231 and 232 having different widths and the connecting portion 234 may be L-shaped, T-shaped, or cross-shaped. It is known that when a force is applied to the wiring 230 including the portions 231 and 232 having different widths, stress concentrates on the connecting portion 234.

連結部分２３４とオーバーラップする位置（連結部分２３４の上方）にはパッド２４０が配置されている。パッド２４０は、集積回路に電気的に接続される。パッド２４０は、ＴｉＮ又はＴｉＷ等からなるバリアメタル層を最上層に含んでもよい。バリアメタル層は、その上に形成される部材の材料がパッド２４０内に拡散することを防止することができる。パッド２４０は、スパッタリングによって形成することができる。   A pad 240 is disposed at a position overlapping the connecting portion 234 (above the connecting portion 234). The pad 240 is electrically connected to the integrated circuit. The pad 240 may include a barrier metal layer made of TiN or TiW as the uppermost layer. The barrier metal layer can prevent the material of the member formed thereon from diffusing into the pad 240. The pad 240 can be formed by sputtering.

パッド２４０を一部として含む配線は、パッド２４０の少なくとも一部（例えば中央部）を除いて、パッシベーション膜２４２に覆われている。パッシベーション膜２４２は、ＳｉＯ2、ＳｉＮなどの無機材料から形成されている。無機材料は、Ａｕ、Ａｌなどの金属よりも硬いことで知られている。 The wiring including the pad 240 as a part is covered with the passivation film 242 except for at least a part of the pad 240 (for example, the central part). The passivation film 242 is made of an inorganic material such as SiO 2 or SiN. Inorganic materials are known to be harder than metals such as Au and Al.

パッド２４０上にはバンプ２４４が形成されている。バンプ２４４は、Ａｕなどの金属から形成されている。Ａｕは、ＴｉＮ又はＴｉＷよりも柔らかい。バンプ２４４は、その一部がパッシベーション膜２４２上に載っていてもよい。バンプ２４４は、電解メッキで形成することができる。   Bumps 244 are formed on the pads 240. The bump 244 is made of a metal such as Au. Au is softer than TiN or TiW. A part of the bump 244 may be placed on the passivation film 242. The bump 244 can be formed by electrolytic plating.

連結部分２３４とパッド２４０との間には、緩衝層２５０が配置されている。緩衝層２５０は、連結部分２３４の全体を覆うように形成されている。配線２３０と緩衝層２５０との間及び緩衝層２５０とパッド２４０との間に、それぞれ、無機絶縁層２６０，２６２が形成されている。無機絶縁層２６０，２６２は、酸化膜などの無機材料から形成されており、無機材料はＡｕ、Ａｌなどの金属よりも硬いことで知られている。緩衝層２５０は、樹脂を除く材料であって、無機絶縁層２６０，２６２よりも柔らかい材料（例えば金属）から形成されている。緩衝層２５０は、配線２３０及びパッド２４０の少なくとも一方と同じ材料で形成してもよい。   A buffer layer 250 is disposed between the connecting portion 234 and the pad 240. The buffer layer 250 is formed so as to cover the entire connecting portion 234. Inorganic insulating layers 260 and 262 are formed between the wiring 230 and the buffer layer 250 and between the buffer layer 250 and the pad 240, respectively. The inorganic insulating layers 260 and 262 are formed of an inorganic material such as an oxide film, and the inorganic material is known to be harder than a metal such as Au or Al. The buffer layer 250 is a material excluding resin, and is made of a material (for example, metal) softer than the inorganic insulating layers 260 and 262. The buffer layer 250 may be formed of the same material as at least one of the wiring 230 and the pad 240.

本実施の形態によれば、幅の異なる部分の連結部分２３４に対してバンプ２４４から力が加えられても、緩衝層２５０によって力が吸収されるので、連結部分２３４に生じる応力を減らすことができる。   According to the present embodiment, even if a force is applied from the bump 244 to the connecting portion 234 of a portion having a different width, the force is absorbed by the buffer layer 250, so that the stress generated in the connecting portion 234 can be reduced. it can.

（第４の実施の形態）
図５（Ａ）は、本発明の第４の実施の形態に係る半導体装置の一部を示す断面図である。図５（Ｂ）は、図５（Ａ）に示す半導体装置の一部を示す平面図である。 (Fourth embodiment)
FIG. 5A is a cross-sectional view showing a part of a semiconductor device according to the fourth embodiment of the present invention. FIG. 5B is a plan view illustrating part of the semiconductor device illustrated in FIG.

この例では、緩衝層３５０は、導電材料から形成され、配線３３０に電気的に接続されていている。詳しくは、緩衝層３５０と配線３３０の間にコンタクト部２７０が設けられて電気的な接続が図られている。また、配線３３０は、幅の異なる部分３３１，３３２の第１の連結部分３３４と、幅の異なる部分３３２，３３３の第２の連結部分３３５と、を有する。幅の異なる部分３３２，３３３において、コンタクト部２７０を設けるために、一方の部分３３３が他方の部分３３２よりも幅が広くなっている。緩衝層３５０は、第１及び第２の連結部分３３４，３３５の両方の全体を覆うように形成されている。その他の構成は、上述した実施の形態で説明した内容が該当し、その作用効果についても同じである。   In this example, the buffer layer 350 is made of a conductive material and is electrically connected to the wiring 330. Specifically, a contact portion 270 is provided between the buffer layer 350 and the wiring 330 to achieve electrical connection. In addition, the wiring 330 includes a first connection portion 334 of portions 331 and 332 having different widths, and a second connection portion 335 of portions 332 and 333 having different widths. In the portions 332 and 333 having different widths, one portion 333 is wider than the other portion 332 in order to provide the contact portion 270. The buffer layer 350 is formed so as to cover both the first and second coupling portions 334 and 335. The other configurations correspond to the contents described in the above-described embodiment, and the same effects are obtained.

本発明は、上述した実施の形態に限定されるものではなく、種々の変形が可能である。例えば、本発明は、実施の形態で説明した構成と実質的に同一の構成（例えば、機能、方法及び結果が同一の構成、あるいは目的及び結果が同一の構成）を含む。また、本発明は、実施の形態で説明した構成の本質的でない部分を置き換えた構成を含む。また、本発明は、実施の形態で説明した構成と同一の作用効果を奏する構成又は同一の目的を達成することができる構成を含む。また、本発明は、実施の形態で説明した構成に公知技術を付加した構成を含む。   The present invention is not limited to the above-described embodiments, and various modifications can be made. For example, the present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same purposes and results). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

図１（Ａ）は、本発明の第１の実施の形態に係る半導体装置の一部を示す断面図であり、図１（Ｂ）は、図１（Ａ）に示す半導体装置の一部を示す平面図である。1A is a cross-sectional view illustrating a part of the semiconductor device according to the first embodiment of the present invention, and FIG. 1B illustrates a part of the semiconductor device illustrated in FIG. FIG. 図２（Ａ）及び図２（Ｂ）は、図１（Ｂ）に示す半導体装置の変形例を示す図である。2A and 2B are diagrams illustrating modifications of the semiconductor device illustrated in FIG. 図３（Ａ）及び図３（Ｂ）は、本発明の第２の実施の形態に係る半導体装置の一部を図であり、図３（Ａ）は、図３（Ｂ）に示すIIIA−IIIA線断面図である。3A and 3B are diagrams illustrating a part of the semiconductor device according to the second embodiment of the present invention, and FIG. 3A is a cross-sectional view taken along the line IIIA- in FIG. 3B. It is a IIIA sectional view. 図４（Ａ）は、本発明の第３の実施の形態に係る半導体装置の一部を示す断面図であり、図４（Ｂ）は、図４（Ａ）に示す半導体装置の一部を示す平面図である。4A is a cross-sectional view illustrating a part of the semiconductor device according to the third embodiment of the present invention, and FIG. 4B illustrates a part of the semiconductor device illustrated in FIG. FIG. 図５（Ａ）は、本発明の第４の実施の形態に係る半導体装置の一部を示す断面図であり、図５（Ｂ）は、図５（Ａ）に示す半導体装置の一部を示す平面図である。FIG. 5A is a cross-sectional view illustrating a part of the semiconductor device according to the fourth embodiment of the present invention, and FIG. 5B illustrates a part of the semiconductor device illustrated in FIG. FIG.

符号の説明Explanation of symbols

１０…半導体チップ、 ２０…電界効果トランジスタ、 ２５…ゲート電極、 ２６…チャネル、 ３０…配線、 ３４…連結部分、 ４０…パッド、 ４２…パッシベーション膜、 ４４…バンプ、 ５０…緩衝層、 ７０…コンタクト部、 １１０…半導体装置、 １３４…連結部分、 １４０…パッド、 １５０…緩衝層、 ２１０…半導体チップ、 ２２０…電界効果トランジスタ、 ２２３…コンタクト部、 ２２５…ゲート電極、 ２２６…チャネル、 ２３０…配線、 ２３２…部分、 ２３４…連結部分、 ２４０…パッド、 ２４２…パッシベーション膜、 ２４４…バンプ、 ２５０…緩衝層、 ２７０…コンタクト部、 ３３０…配線、 ３３４…第１の連結部分、 ３３５…第２の連結部分、 ３５０…緩衝層   DESCRIPTION OF SYMBOLS 10 ... Semiconductor chip, 20 ... Field effect transistor, 25 ... Gate electrode, 26 ... Channel, 30 ... Wiring, 34 ... Connection part, 40 ... Pad, 42 ... Passivation film, 44 ... Bump, 50 ... Buffer layer, 70 ... Contact 110, a semiconductor device, 134, a connecting portion, 140, a pad, 150, a buffer layer, 210, a semiconductor chip, 220, a field effect transistor, 223, a contact portion, 225, a gate electrode, 226, a channel, 230, a wiring, 232 ... part, 234 ... connection part, 240 ... pad, 242 ... passivation film, 244 ... bump, 250 ... buffer layer, 270 ... contact part, 330 ... wiring, 334 ... first connection part, 335 ... second connection Part, 350 ... buffer layer

Claims (4)

半導体チップと、
前記半導体チップに作り込まれてなる、幅の異なる部分の連結部分を有する配線と、
前記配線の上方であって、前記連結部分とオーバーラップする位置に形成されたパッドと、
前記パッド上に形成されてなるバンプと、
前記連結部分と前記パッドとの間に位置して前記連結部分の全体を覆うように形成されてなる緩衝層と、
前記配線と前記緩衝層との間及び前記緩衝層と前記パッドとの間に、それぞれ形成されてなる無機絶縁層と、
を含み、
前記緩衝層は、樹脂を除く材料であって、前記無機絶縁層よりも柔らかい材料から形成されてなる半導体装置。 A semiconductor chip;
A wiring formed in the semiconductor chip and having a connecting portion of different widths;
A pad formed above the wiring and at a position overlapping the connecting portion;
A bump formed on the pad;
A buffer layer formed between the connecting portion and the pad so as to cover the entire connecting portion;
An inorganic insulating layer formed between the wiring and the buffer layer and between the buffer layer and the pad;
Including
The buffer layer is a semiconductor device formed of a material excluding resin and softer than the inorganic insulating layer. 請求項１に記載された半導体装置において、
前記配線は抵抗素子として用いられる半導体装置。 The semiconductor device according to claim 1,
The wiring is a semiconductor device used as a resistance element. 請求項１又は請求項２のいずれかに記載された半導体装置において、
前記緩衝層は、導電材料から形成され、前記配線に電気的に接続されてなる半導体装置。 In the semiconductor device according to claim 1 or 2,
The buffer layer is a semiconductor device formed of a conductive material and electrically connected to the wiring. 請求項１乃至請求項３のいずれかに記載された半導体装置において、
前記配線はポリシリコンによって形成されてなる半導体装置。 The semiconductor device according to any one of claims 1 to 3,
A semiconductor device in which the wiring is made of polysilicon.
JP2007305584A 2007-11-27 2007-11-27 Semiconductor device Active JP4835873B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007305584A JP4835873B2 (en) 2007-11-27 2007-11-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007305584A JP4835873B2 (en) 2007-11-27 2007-11-27 Semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP2006128360A Division JP4072697B2 (en) 2006-05-02 2006-05-02 Semiconductor device

Publications (3)

Publication Number Publication Date
JP2008066760A true JP2008066760A (en) 2008-03-21
JP2008066760A5 JP2008066760A5 (en) 2008-05-08
JP4835873B2 JP4835873B2 (en) 2011-12-14

Family

ID=39289125

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007305584A Active JP4835873B2 (en) 2007-11-27 2007-11-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JP4835873B2 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6422039A (en) * 1987-07-17 1989-01-25 Hitachi Ltd Semiconductor device
JPH11307724A (en) * 1998-04-21 1999-11-05 Rohm Co Ltd Semiconductor integrated circuit
JP2002319587A (en) * 2001-04-23 2002-10-31 Seiko Instruments Inc Semiconductor device
JP2006013276A (en) * 2004-06-29 2006-01-12 Nec Kansai Ltd Semiconductor device and its manufacturing method
JP2007087975A (en) * 2005-09-16 2007-04-05 Ricoh Co Ltd Semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6422039A (en) * 1987-07-17 1989-01-25 Hitachi Ltd Semiconductor device
JPH11307724A (en) * 1998-04-21 1999-11-05 Rohm Co Ltd Semiconductor integrated circuit
JP2002319587A (en) * 2001-04-23 2002-10-31 Seiko Instruments Inc Semiconductor device
JP2006013276A (en) * 2004-06-29 2006-01-12 Nec Kansai Ltd Semiconductor device and its manufacturing method
JP2007087975A (en) * 2005-09-16 2007-04-05 Ricoh Co Ltd Semiconductor device

Also Published As

Publication number Publication date
JP4835873B2 (en) 2011-12-14

Similar Documents

Publication Publication Date Title
JP4072697B2 (en) Semiconductor device
US20230253358A1 (en) Bump-on-Trace Design for Enlarge Bump-to-Trace Distance
JP2005347622A (en) Semiconductor device, circuit board and electronic equipment
TWI588959B (en) Semiconductor device
US7999395B1 (en) Pillar structure on bump pad
JP4835873B2 (en) Semiconductor device
JP2007287984A (en) Semiconductor device
JP2009266998A (en) Semiconductor device and method of manufacturing the same
JP2008010778A (en) Semiconductor device
WO2023189480A1 (en) Semiconductor element and semiconductor device
JP4835230B2 (en) Mounting structure of semiconductor device
JP2015204393A (en) semiconductor device
JP5263469B2 (en) Semiconductor device
US10910330B2 (en) Pad structure and integrated circuit die using the same
JP2006179916A (en) Semiconductor element having passivation layer
JP6899233B2 (en) Magnetron conversion element and magnetron conversion module
JP2004228321A (en) Semiconductor device and its design method
JP2005294678A (en) Semiconductor device, and manufacturing method thereof
JP2006222395A (en) Semiconductor device
JPH04370943A (en) Semiconductor integrated circuit device
JPH06349825A (en) Semiconductor integrated circuit device
JPH03284847A (en) Semiconductor device

Legal Events

Date Code Title Description
A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080325

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080325

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20080703

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20110307

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110316

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110513

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110608

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110803

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20110831

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110913

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20141007

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 4835873

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350