JP2008010778A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To implement a semiconductor device capable of alleviating concentration of thermal stress in an external connection electrode. <P>SOLUTION: The semiconductor device comprises a passivation film 12 formed to cover the entire surface of a semiconductor chip 11; an electrode pad 13 formed in the passivation film 12 to provide external electrical connection; an opening formed by removing the passivation film 12 on the electrode pad 13; a barrier metal 14 formed to cover the opening and passivation film 12 around the opening, wherein the distance of an adhesive surface differs between a portion near the center of the semiconductor chip 11 and a portion opposite thereto, on a line connecting the center of the semiconductor chip 11 and center of the opening; and a metal bump 15 formed on the barrier metal 14 as an external electrode. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a structure of an external connection electrode in a semiconductor device, and more particularly to a flip-chip under-bump electrode structure.

  Due to the downsizing and higher performance of electronic products, semiconductor devices have become faster and more terminals. High-speed multi-terminal semiconductor devices usually require a flip chip connection package structure, but it is well known that a large thermal stress is generated in the external connection electrode due to the difference between the thermal expansion coefficient of the substrate and the thermal expansion coefficient of the chip ( For example, see “Patent Document 1”). Further, a solder material with a rounded edge is usually used for the external connection terminal of the flip chip. However, in recent years, it has become necessary to make lead-free due to environmental considerations. Lead of the solder material has an effect of lowering the melting point and relieving stress. For this reason, due to the lead-free design, the stress due to the difference in thermal expansion coefficient between the substrate and the chip concentrates on the connection part, particularly the electrode part. Furthermore, (1) the dielectric constant of the insulating layer is lowered for the purpose of improving the electrical characteristics of the wiring in the semiconductor chip, leading to the weakening of the insulating layer, and (2) the electrode terminals due to the miniaturization of the external connection terminals. (3) Since the distance between the electrode terminals is close due to miniaturization, the connection height is lowered, and this also tends to cause stress concentration. For this reason, a method for reducing the stress concentration in the external connection electrode is required.

  FIG. 7 is a cross-sectional view showing the structure of an external connection electrode in a conventional semiconductor device. FIG. 7 shows a case where the flip chip 102 is bonded onto the substrate 103 via the solder bumps 101 as an example. As shown in FIG. 7, the external connection electrode of the flip chip 102 is formed on a barrier metal 106 on an aluminum (Al) electrode pad 105 provided in a passivation film 104 formed so as to cover the surface of the flip chip 102. (Hereinafter referred to as “UBM layer 106”), and solder bumps 101 are bonded to the UBM layer 106. The UBM layer 106 is formed so as to cover the opening from which the passivation film 104 has been removed in order to connect to the electrode pad 105 and its periphery.

Here, a case where the temperatures of the flip chip 102 and the substrate 103 change from a high temperature to a low temperature (the thermal stress due to the difference in thermal expansion coefficient between the substrate 103 and the flip chip 102 is maximized in this case) is considered. At this time, as shown in FIG. 7, the flip chip 102 has a small thermal contraction due to the temperature difference, while the substrate 103 has a large thermal contraction due to the temperature difference. Therefore, the thermal stress due to the difference in thermal expansion coefficient between the substrate 103 and the flip chip 102 is the corner of the UBM layer 106 on the opposite side as viewed from the chip center (left side in FIG. 7) (the part surrounded by a thick frame in FIG. 7). .) Tensile stress concentrates. For this reason, the conventional external electrode structure in the semiconductor device has a problem that the UBM layer 106 on the opposite side as viewed from the center of the chip is easily peeled off from the passivation film 104.
JP-A-6-177134

  The present invention provides a semiconductor device that can alleviate concentration of thermal stress in an external connection electrode.

  According to one aspect of the present invention, a passivation film formed so as to cover the entire surface of the semiconductor chip, an electrode pad formed in the passivation film for electrical connection with the outside, and the electrode pad An opening formed by removing the passivation film, and a straight line connecting the center of the semiconductor chip and the center of the opening, and is formed so as to cover the opening and the passivation film around the opening. A semiconductor device comprising: a barrier metal having a distance of an adhesion portion between the central side of the semiconductor chip and the opposite side to the passivation film; and a metal bump formed on the barrier metal as an external electrode. Is provided.

  According to the present invention, since the concentration of thermal stress in the external connection electrode can be reduced, a semiconductor device having a fine and reliable external connection electrode can be realized.

  Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing the structure of an external connection electrode in a semiconductor device according to an embodiment of the present invention.
The structure of the external connection electrode in the semiconductor device according to the embodiment of the present invention includes a passivation film 12 formed so as to cover the surface of the chip 11, an aluminum pad 13 formed in the passivation film 12, and an opening on the aluminum pad 13. A barrier metal 14 (hereinafter referred to as “UBM layer 14”) formed so as to cover the portion and its periphery, and a metal bump 15 bonded to the UBM layer 14.

  The passivation film 12 is composed of a passivation film made of a semiconductor inorganic material and a passivation film made of an organic material formed thereon.

  The aluminum pad 13 is formed in the passivation film 12, and a part of the passivation film 12 on the aluminum pad 13 is removed for connection with the outside to form an opening.

  The UBM layer 14 is a circular conductive film formed so as to cover the opening and its periphery. The UBM layer 14 is bonded to the aluminum pad 13 at the bottom of the opening, and is bonded to the passivation film 12 at the periphery of the opening. . A metal bump 15 is bonded to almost the entire surface of the UBM layer 14.

FIG. 2 is a schematic view showing the bonding surface of the UBM layer 14 in the semiconductor device according to the embodiment of the present invention.
As shown in FIG. 2, the pad bonding surface 21 between the UBM layer 14 and the aluminum pad 13 is a straight line connecting the center of the chip 11 (on the right side in FIG. 2) and the center of the UBM layer 14. It is formed to be shifted toward the center side of the chip 11 along the center line. That is, the opening on the pad bonding surface 21, that is, the aluminum pad 13 is formed so that a <b, where a is the distance on the center side of the chip 11 of the passivation bonding surface 22 and b is the distance on the opposite side. . The UBM layer 14 is formed so that a is at least 10 μm or more.

  Further, the pad bonding surface 21 has an area Smin secured in consideration of the EM (electromigration) limit.

FIG. 3 is a graph showing the relationship between the adhesion area and the current density in the UBM layer 14 of the semiconductor device according to the example of the present invention.
The vertical axis of the graph indicates the current density on the pad bonding surface 21 on an arbitrary scale, and the horizontal axis indicates the area of the pad bonding surface 21 on an arbitrary scale. Since the EM limit is determined by the maximum current flowing through the external connection electrode, as shown in FIG. 3, the area of the pad bonding surface 21 has a minimum area Smin required by specifications.

  FIG. 4 is a distribution diagram showing the stress of the UBM layer 14 in the semiconductor device according to the embodiment of the present invention. Here, as an example, the stress distribution in the cross section near the UBM layer 14 when the flip chip 11 having the electrode structure of FIG. 1 is mounted on the substrate 41 is shown.

  As shown in FIG. 4, the stress distribution in the UBM layer 14 is concentrated in the corner on the opposite side as viewed from the center side of the chip 11 (left side in FIG. 4).

  FIG. 5 is a graph showing changes in stress in the semiconductor device according to the example of the present invention. Here, three types of structures having different adhesion distances b between the UBM layer 14 and the passivation film 12 were simulated, and the results were shown as stresses along the center line (FIGS. 4A to 4C).

  The vertical axis in FIG. 5 represents stress, and the horizontal axis represents the distance from the corner of the passivation bonding surface 22 on an arbitrary scale.

  As can be seen from FIG. 5, the connection stress of the UBM layer 14 decreases as the distance b between the UBM layers 14 formed on the passivation film 12 increases. On the other hand, when the distance b is reduced, high stress is generated in the fragile insulating layer on the chip 11, leading to peeling and destruction.

  According to the above embodiment, the concentration of the thermal stress in the external connection electrode is reduced by increasing the distance of the bonding surface between the UBM layer 14 and the passivation film 12 on the opposite side as viewed from the center of the chip 11 from the center side of the chip 11. Therefore, a semiconductor device having a fine and highly reliable external connection electrode can be realized.

  In the above embodiment, the pad bonding surface 21 and the passivation bonding surface 22 are both circular, but the present invention is not limited to this. For example, as shown in FIG. Conceivable. 6A, the passivation bonding surface 22 has an oval shape along the center line, and FIG. 6B has the pad bonding surface 21 formed in an oval shape along a direction perpendicular to the center line. ) Has the pad bonding surface 21 similarly rectangular. In either case, the area b of the pad bonding surface 21 is maintained to be equal to or greater than Smin, and the distance b of the passivation bonding surface 22 is increased.

  In the above-described embodiment, the chip 11 is mounted on the substrate. However, the present invention is not limited to this. For example, the present invention is also applicable to a case where a plurality of chips 11 are stacked to form the laminated chip 11. can do. In such a case, since the distribution of thermal stress changes depending on the size and thickness of the chips 11 to be stacked, a <b is not always satisfied. In some cases, the stress applied to the UBM layer 14 can be relaxed by setting a> b.

Sectional drawing which shows the structure of the external connection electrode in the semiconductor device concerning the Example of this invention. The schematic diagram which shows the adhesion surface of the UBM layer 14 in the semiconductor device concerning the Example of this invention. The graph which shows the relationship between the adhesion area and current density in the UBM layer of the semiconductor device concerning the Example of this invention. The distribution map which shows the stress of the UBM layer 14 in the semiconductor device concerning the Example of this invention. The graph which shows the change of the stress in the semiconductor device concerning the Example of this invention. The schematic diagram which shows the other adhesion surface of the UBM layer 14 in the semiconductor device concerning the Example of this invention. Sectional drawing which shows the structure of the external connection electrode in the conventional semiconductor device.

Explanation of symbols

11 Chip 12 Passivation film 13 Aluminum pad 14 Barrier metal (UBM layer)
15 Metal bump

Claims (3)

A passivation film formed to cover the entire surface of the semiconductor chip;
An electrode pad formed in the passivation film for electrical connection with the outside;
An opening formed by removing the passivation film on the electrode pad;
The passivation is formed so as to cover the opening and the passivation film around the opening, and on the straight line connecting the center of the semiconductor chip and the center of the opening on the center side of the semiconductor chip and the opposite side thereof. Barrier metals with different distances between the adhesive part and the film,
A semiconductor device comprising metal bumps formed on the barrier metal as external electrodes.   2. The semiconductor device according to claim 1, wherein a distance of an adhesion portion between the barrier metal and the passivation film is larger on the opposite side than on the center side of the semiconductor chip.   2. The semiconductor device according to claim 1, wherein a distance of an adhesion portion between the barrier metal and the passivation film is at least 10 μm or more.

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