JP2005057125A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2005057125A
JP2005057125A JP2003287813A JP2003287813A JP2005057125A JP 2005057125 A JP2005057125 A JP 2005057125A JP 2003287813 A JP2003287813 A JP 2003287813A JP 2003287813 A JP2003287813 A JP 2003287813A JP 2005057125 A JP2005057125 A JP 2005057125A
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Prior art keywords
semiconductor device
integrated circuit
metal
metal film
semiconductor
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Japanese (ja)
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Kenji Otani
憲司 大谷
Masahiro Tsuji
正博 辻
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to JP2003287813A priority Critical patent/JP2005057125A/en
Priority to KR1020040060778A priority patent/KR20050016087A/en
Priority to CNB2004101047336A priority patent/CN100386870C/en
Priority to US10/911,509 priority patent/US20050212148A1/en
Priority to TW093123585A priority patent/TWI346369B/en
Publication of JP2005057125A publication Critical patent/JP2005057125A/en
Priority to US11/468,693 priority patent/US20070120236A1/en
Priority to US11/469,225 priority patent/US20070063334A1/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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  • Semiconductor Integrated Circuits (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the resistance of a power source or grounding wiring when a semiconductor device is mounted on a circuit board. <P>SOLUTION: In order to minimize the distance from the power source and/or grounding line of the semiconductor integrated circuit 10 of the semiconductor device 1 to the electrode of the circuit board, at least either one of the power supply electrode and grounding line of the semiconductor integrated circuit 10 is connected to a metallic film 30 through the opening of a protective film 26 formed on the electrode. The metallic film 30 is exposed on the circuit board side on which the semiconductor device 1 is mounted or on the opposite side, and connected to the power source and/or grounding electrode of the circuit board through the exposed surface. Alternatively, the metallic film 30 is constituted of upper and lower metallic films connected to each other through a stress relieving film interposed between the metallic films, or a metallic sheet is disposed on the metallic film 30. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、プリント回路基板等の回路基板に配置したときの配線抵抗を低減させた半導体装置に関する。   The present invention relates to a semiconductor device with reduced wiring resistance when placed on a circuit board such as a printed circuit board.

従来の半導体装置では、半導体集積回路の内部電極であるグランド或いは電源電極の取り出し口は半導体集積回路の周辺部に配置されるのが一般的であり、そのため半導体集積回路の内部の素子から非常に細いアルミニュウムや銅の金属配線で半導体集積回路の周辺部に配置された電極取り出し口に接続する必要があった。また、半導体集積回路の電極取り出し口とプリント回路基板等の回路基板の電極との接続は、半導体集積回路の電極と銅合金等のリードと呼ばれ金属板或いはバンプ又はランドを金あるいはアルミニュウム又は銅のワイヤーで接合するか、又は金、はんだ、スズ等のバンプで接合して行い、かつ半導体集積回路、半導体集積回路の電極とリード、バンプ、又はランドとの接合部、リード又はバンプ又はランド等を機械的ストレス等から保護するため、エポキシ樹脂、ポリイミドなどの合成樹脂で封止している。
なお、稀には半導体集積回路の中央付近に内部電極の取り出し口を設け、そこからワイヤーでリードに接続する場合もある。 In a conventional semiconductor device, a ground or power supply electrode, which is an internal electrode of a semiconductor integrated circuit, is generally arranged at a peripheral portion of the semiconductor integrated circuit. It was necessary to connect to the electrode lead-out port arranged in the peripheral part of the semiconductor integrated circuit with thin aluminum or copper metal wiring. In addition, the connection between the electrode outlet of the semiconductor integrated circuit and the electrode of the circuit board such as a printed circuit board is called a lead of a semiconductor integrated circuit and a copper alloy or the like, and a metal plate or bump or land is made of gold, aluminum or copper. Bonded with a wire, or bonded with a bump such as gold, solder, tin, etc., and a semiconductor integrated circuit, a junction between a semiconductor integrated circuit electrode and a lead, bump, or land, a lead, bump, or land Is sealed with a synthetic resin such as epoxy resin or polyimide.
In rare cases, a lead-out port for the internal electrode may be provided near the center of the semiconductor integrated circuit, and the lead may be connected to the lead from there.

図９は、特定の文献に記載されたものではないが従来の半導体装置１の１例を模式的に示す断面図である。半導体装置１の半導体集積回路１０は接着剤又ははんだによりダイパッド１２上に取り付けられており、かつ図中上部、即ちその能動面上には保護膜２６が形成されていると共に、その保護膜２６の複数の電極取り出し口２２，２４を通して半導体集積回路１０の一端が内部電極に接続された金属配線２０の他端に接続されたワイヤー１８がリード１６に接続されており、かつエポキシ樹脂等で樹脂封止１８されている。   FIG. 9 is a cross-sectional view schematically showing an example of a conventional semiconductor device 1 that is not described in a specific document. The semiconductor integrated circuit 10 of the semiconductor device 1 is attached to the die pad 12 by an adhesive or solder, and a protective film 26 is formed on the upper portion of the drawing, that is, on the active surface thereof. A wire 18 connected to the other end of the metal wiring 20 in which one end of the semiconductor integrated circuit 10 is connected to the internal electrode through the plurality of electrode outlets 22 and 24 is connected to the lead 16 and is sealed with epoxy resin or the like. Stopped 18

このように従来の半導体装置１は、半導体集積回路１０の内部電極（内部素子）から半導体集積回路の周辺部に配置された電極取り出し口２２まで非常に細い金属配線２０で接続し、かつ半導体集積回路１０の電極取り出し口２２，２４からワイヤー１８でリード１６に接続する必要があったため、配線長が長くなり、その分電気抵抗値の増加を招き、特性劣化の要因となっていた。
また、半導体集積回路の中央付近に電極取り出し口を設けた構造の半導体集積回路では、前記構造の半導体装置よりも配線抵抗を若干低減することができるが、電極取り出し口とリードとを金属細線で接続しなければならずかつその細線長が長くなるため、いずれにしろ電気抵抗値の増大を招き、特性劣化の要因となっていた。
加えて、近年は半導体集積回路の微細化が益々進んだ結果、金属配線、金属細線は益々細くなる傾向にあるため、この要因による特性劣化も益々顕著になりつつある。
なお、半導体装置において、ＩＣチップに金属突起（金属バンプ）を設け、この金属突起に金属部材（金属棒）を載置して、両者を例えば非導電性接着等で固定して、金属棒端部を露出させた構造の半導体装置が知られているが（特許文献１参照）、これは専ら放熱を目的としたものであって、金属棒はＩＣチップの電極に接続されてものではない。 As described above, the conventional semiconductor device 1 is connected by the very thin metal wiring 20 from the internal electrode (internal element) of the semiconductor integrated circuit 10 to the electrode lead-out port 22 arranged in the peripheral part of the semiconductor integrated circuit, and is integrated in the semiconductor integrated circuit. Since it was necessary to connect to the lead 16 by the wire 18 from the electrode outlets 22 and 24 of the circuit 10, the wiring length was increased, and the electrical resistance value was increased correspondingly, which caused deterioration of characteristics.
Further, in a semiconductor integrated circuit having a structure in which an electrode lead-out port is provided near the center of the semiconductor integrated circuit, the wiring resistance can be slightly reduced as compared with the semiconductor device having the above structure, but the electrode lead-out port and the lead are made of thin metal wires. Since it has to be connected and the length of the thin wire becomes long, the electrical resistance value is increased anyway, which causes deterioration of characteristics.
In addition, in recent years, as the miniaturization of semiconductor integrated circuits has progressed, metal wiring and metal thin wires tend to become thinner. Therefore, characteristic deterioration due to this factor is becoming more and more remarkable.
In a semiconductor device, a metal protrusion (metal bump) is provided on an IC chip, a metal member (metal bar) is placed on the metal protrusion, and both are fixed by, for example, non-conductive bonding, and the end of the metal bar A semiconductor device having a structure in which a portion is exposed is known (see Patent Document 1), but this is exclusively for heat dissipation, and the metal rod is not connected to the electrode of the IC chip.

特開平７−６６３３２号公報JP-A-7-66332

本発明は従来の半導体装置における上記問題を解決すべくなされたものであって、その目的は、半導体装置の半導体集積回路内部の素子からプリント基板等の外部端子までの配線抵抗を大幅に改善し、特性劣化を最小限に止めることである。   The present invention has been made to solve the above-mentioned problems in conventional semiconductor devices, and its purpose is to greatly improve the wiring resistance from the elements inside the semiconductor integrated circuit of the semiconductor device to the external terminals such as a printed circuit board. It is to minimize the deterioration of characteristics.

上記目的を達成するため、
請求項１の発明は、半導体集積回路と、該半導体集積回路の電極端子と基板電極とを接続する導電手段を有し、樹脂封止した半導体装置において、上記半導体集積回路上に順に積層して設けた保護膜及び金属膜を有し、該金属膜が上記保護膜の開孔部分で半導体集積回路の内部電極と接続し、かつ該金属膜を上記半導体装置の表面若しくは裏面側で上記封止樹脂から露出させたことを特徴とする半導体装置である。
請求項２の発明は、請求項１に記載された半導体装置において、上記金属膜が応力緩和層を備えていることを特徴とする半導体装置である。
請求項３の発明は、請求項２に記載された半導体装置において、上記金属膜は第１及び第２の金属膜からなり、該第１及び第２の金属膜は上記応力緩和層を介在させて少なくとも１箇所で接続されており、上記第２の金属膜を半導体装置の表面、若しくは裏面側で上記封止樹脂から露出させたことを特徴とする半導体装置である。
請求項４の発明は、請求項１に記載された半導体装置において、上記第１の金属膜に接合された金属板を有し、かつ該金属板を上記半導体装置の表面若しくは裏面側で封止樹脂から露出させたことを特徴とする半導体装置である。
請求項５の発明は、請求項２又は３に記載された半導体装置において、上記第２の金属膜に接合された金属板を有し、かつ該金属板を上記半導体装置の表面若しくは裏面側で封止樹脂から露出させたことを特徴とする半導体装置である。
請求項６の発明は、請求項１ないし５のいずれかに記載された半導体装置において、上記第１及び第２の金属膜は金、アルミニュウム、銅又はそれを主成分とする合金からなり、上記応力緩和層はポリイミド、エポキシ樹脂、その他のエラストマー又はプラストマーであることを特徴とする半導体装置である。
請求項７の発明は、請求項１ないし６に記載された半導体装置において、半導体集積回路を搭載したダイパッドを有し、該ダイパッドを半導体装置の表面若しくは裏面側で上記封止樹脂から露出させたことを特徴とする半導体装置である。
請求項８の発明は、請求項１ないし７のいずれかに記載された半導体装置において、半導体装置の表面あるいは裏面側で上記封止樹脂から露出させた金以外の金属膜又は金属板の表面にメッキ層を有することを特徴とする半導体装置である。 To achieve the above objective,
The invention according to claim 1 is a semiconductor device having a semiconductor integrated circuit and conductive means for connecting an electrode terminal of the semiconductor integrated circuit and a substrate electrode, and is sequentially laminated on the semiconductor integrated circuit in a resin-sealed semiconductor device. A protective film and a metal film provided; the metal film is connected to an internal electrode of the semiconductor integrated circuit at an opening portion of the protective film; and the metal film is sealed on the front or back side of the semiconductor device. A semiconductor device characterized by being exposed from a resin.
According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the metal film includes a stress relaxation layer.
According to a third aspect of the present invention, in the semiconductor device of the second aspect, the metal film includes first and second metal films, and the first and second metal films interpose the stress relaxation layer. The semiconductor device is characterized in that the second metal film is exposed from the sealing resin on the front surface or the back surface side of the semiconductor device.
According to a fourth aspect of the present invention, in the semiconductor device according to the first aspect, the semiconductor device includes a metal plate bonded to the first metal film, and the metal plate is sealed on the front surface or the back surface side of the semiconductor device. A semiconductor device characterized by being exposed from a resin.
According to a fifth aspect of the present invention, in the semiconductor device according to the second or third aspect, the semiconductor device includes a metal plate bonded to the second metal film, and the metal plate is disposed on the front surface or the back surface side of the semiconductor device. A semiconductor device characterized by being exposed from a sealing resin.
According to a sixth aspect of the present invention, in the semiconductor device according to any one of the first to fifth aspects, the first and second metal films are made of gold, aluminum, copper, or an alloy mainly containing the metal film. The stress relaxation layer is a semiconductor device characterized by being made of polyimide, epoxy resin, other elastomer or plastomer.
According to a seventh aspect of the present invention, in the semiconductor device according to any one of the first to sixth aspects, the semiconductor device further includes a die pad on which a semiconductor integrated circuit is mounted, and the die pad is exposed from the sealing resin on a front surface or a back surface side of the semiconductor device. This is a semiconductor device.
According to an eighth aspect of the present invention, in the semiconductor device according to any one of the first to seventh aspects, the surface of the semiconductor device is exposed on the surface of the metal film or metal plate other than gold exposed from the sealing resin on the front surface or back surface side. A semiconductor device having a plating layer.

本発明によれば、（１）半導体装置内部の半導体集積回路の任意の場所から内部電極を最短距離で基板電極に接合することが可能となり、配線抵抗を非常に小さくすることができる。これにより高速かつ小型化した半導体装置を安定して動作させることができる。また、金属膜又は金属板により半導体集積回路で発生した熱を効率よく放熱することができる。
（２）金属膜に応力緩和膜を備えることにより、半導体集積回路で発生した熱による半導体装置内部における熱応力を緩和し、結合した各要素間の剥離等による故障を防止することができる。 According to the present invention, (1) the internal electrode can be joined to the substrate electrode from the arbitrary position of the semiconductor integrated circuit inside the semiconductor device at the shortest distance, and the wiring resistance can be extremely reduced. As a result, the semiconductor device reduced in speed and size can be stably operated. Further, the heat generated in the semiconductor integrated circuit can be efficiently radiated by the metal film or the metal plate.
(2) By providing the metal film with the stress relaxation film, the thermal stress inside the semiconductor device due to the heat generated in the semiconductor integrated circuit can be relaxed, and failure due to separation between the coupled elements can be prevented.

本発明の実施形態を図面を参照して説明する。
図１は本発明の実施形態に係る半導体装置を模式的に示す断面図であり、従来のものと同一の箇所には同一の番号を付してある。即ち、半導体装置１の半導体集積回路１０は接着剤又ははんだによりダイパッド１２上に取り付けられており、かつ図中上部、即ちその能動面上には保護膜２６が形成されている。また、その保護膜２６の複数の電極取り出し口２２，２４を介して半導体集積回路１０の金属配線２０に接続されたワイヤー１８がリード１６に接続されており、半導体集積回路１０、ダイパッド１２，ワイヤー１８金属配線２０，保護膜２６等がエポキシ樹脂２８により封止されている。 Embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a cross-sectional view schematically showing a semiconductor device according to an embodiment of the present invention. The same reference numerals are given to the same portions as those of the conventional one. That is, the semiconductor integrated circuit 10 of the semiconductor device 1 is attached on the die pad 12 by an adhesive or solder, and a protective film 26 is formed on the upper portion in the drawing, that is, on the active surface thereof. Further, the wire 18 connected to the metal wiring 20 of the semiconductor integrated circuit 10 is connected to the lead 16 through the plurality of electrode outlets 22 and 24 of the protective film 26, and the semiconductor integrated circuit 10, the die pad 12, the wire 18 Metal wiring 20, protective film 26 and the like are sealed with epoxy resin 28.

ここで、本実施形態では、半導体集積回路１０の能動面には従来の電極取り出し口２２，２４に加えて半導体集積回路１０の任意の場所に半導体集積回路の少なくともグランドライン若しくは電源ラインのどちらか一方を取り出す電極取り出し口３２を一箇所あるいは複数箇所設け、その部分の保護膜２６は除去されている。保護膜２６上には、半導体集積回路１０の外部端子との接続を行う電極取り出し口３２以外の保護膜２６の開孔部を除く部分に、蒸着法、若しくはメッキ法で金、アルミニュウム、銅又はそれらを主成分とする合金でできた金属膜を形成している。形成する金属膜の大きさは、半導体集積回路の外部端子との接続を行う電極取り出し口３２以外の保護膜の開孔部を除く領域の概ね６０〜８０％が望ましい。これにより半導体集積回路のグランドライン又は電源ラインのどちらか一方は保護膜２６の上に形成された金属膜３０と接合される。
この金属膜３０は半導体装置１を覆うエポキシ樹脂２８から露出しており、この露出した金属膜３０とプリント基板の電極（図示せず）とを接続させることにより、従来のように長い金属配線を用いずに半導体集積回路１０の電極（電源又はグランド電極）に接続することができる。また、半導体集積回路１０で発生した熱を金属膜３０を介して外部に放熱することができる。 Here, in the present embodiment, on the active surface of the semiconductor integrated circuit 10, in addition to the conventional electrode lead-out ports 22 and 24, at least either the ground line or the power supply line of the semiconductor integrated circuit is provided at an arbitrary position of the semiconductor integrated circuit 10. One or a plurality of electrode take-out ports 32 for taking out one of them are provided, and the protective film 26 at that portion is removed. On the protective film 26, gold, aluminum, copper, or the like is formed by vapor deposition or plating on a portion other than the opening portion of the protective film 26 other than the electrode extraction port 32 that is connected to the external terminal of the semiconductor integrated circuit 10. A metal film made of an alloy containing them as a main component is formed. The size of the metal film to be formed is preferably approximately 60 to 80% of the region excluding the opening of the protective film other than the electrode extraction port 32 for connection to the external terminal of the semiconductor integrated circuit. As a result, either the ground line or the power supply line of the semiconductor integrated circuit is bonded to the metal film 30 formed on the protective film 26.
The metal film 30 is exposed from the epoxy resin 28 that covers the semiconductor device 1. By connecting the exposed metal film 30 and an electrode (not shown) of the printed circuit board, a long metal wiring as in the prior art is formed. It can be connected to the electrode (power supply or ground electrode) of the semiconductor integrated circuit 10 without using it. Further, the heat generated in the semiconductor integrated circuit 10 can be radiated to the outside through the metal film 30.

図２は本発明の半導体装置の第２の実施形態を示す模式的断面図である。この実施形態では基本構造は図１に示した半導体装置と同様であり、ただ、第１の実施形態に係る半導体装置１における金属膜３０に代えて、半導体集積回路１０と半導体装置１の露出部との応力を緩和するために保護膜２６の上に形成させた金属膜３０ａの上にさらにポリイミド等の応力緩和膜３４を設け、さらにその上に蒸着法、若しくはメッキ法等で例えば、金、アルミニュウム、銅又はこれらを主成分とする合金でできた金属膜３０ｂを形成させている。半導体集積回路からみて上層の金属膜３０ｂは半導体装置１を封止するエポキシ樹脂２８から露出しており、この露出した金属膜３０ｂとプリント基板の電極（図示せず）とを接続させ、下層の金属膜３０ａと上層の金属膜３０ｂは少なくとも１箇所で接続されている。この構成により、前記第１の実施形態と同様に従来のように長い金属配線を用いずに半導体集積回路１０の内部電極（内部素子）を電源又はグランドラインに接続することができるだけでなく、応力緩和層３４を備えているので、動作時と非動作時に半導体装置１が加熱と冷却を繰り返すことで、同装置１内部の各要素間の熱膨張率の差により接合部分が剥離して半導体装置１が破損したり或いは接続不良を起こすなどの問題が生じることはない。   FIG. 2 is a schematic cross-sectional view showing a second embodiment of the semiconductor device of the present invention. In this embodiment, the basic structure is the same as that of the semiconductor device shown in FIG. 1. However, instead of the metal film 30 in the semiconductor device 1 according to the first embodiment, the semiconductor integrated circuit 10 and the exposed portion of the semiconductor device 1 are used. In order to relieve stress, a stress relaxation film 34 such as polyimide is further provided on the metal film 30a formed on the protective film 26, and further, for example, gold, A metal film 30b made of aluminum, copper, or an alloy containing these as a main component is formed. When viewed from the semiconductor integrated circuit, the upper metal film 30b is exposed from the epoxy resin 28 that seals the semiconductor device 1, and the exposed metal film 30b is connected to an electrode (not shown) of the printed circuit board. The metal film 30a and the upper metal film 30b are connected in at least one place. With this configuration, the internal electrode (internal element) of the semiconductor integrated circuit 10 can be connected to the power supply or the ground line without using a long metal wiring as in the conventional case, as in the first embodiment. Since the relaxation layer 34 is provided, the semiconductor device 1 repeats heating and cooling during operation and non-operation, so that the joining portion is peeled off due to the difference in coefficient of thermal expansion between the elements inside the device 1. There will be no problems such as damage to 1 or poor connection.

図３は本発明の半導体装置の第３の実施形態を示す模式的断面図である。この実施形態は、第１の実施形態に係る半導体装置１における金属膜３０上に金、銅などの金属板４０を配置した構造である。この構造は、半導体集積回路１０と半導体装置１の表面、あるいは裏面までに距離があり、金属膜３０で半導体装置１の表面あるいは裏面に露出させるには生産性的にも経済的にも好ましくない場合に好適であって、金属膜の上に例えば、金、アルミニュウム、銅或いはこれらを主成分とする合金でできた金属板を接合して、その金属板を半導体装置の表面あるいは裏面に露出させている。
この構成により、前記第１の実施形態と同様に従来のように長い金属配線を用いずに半導体集積回路１０の内部電極を電源又はグランドラインに接続することができるだけでなく、金属板４０はヒートシンクとして機能するから半導体集積回路で発生した熱を一層促進することができる。また、金属膜３０と金属板４０の接合は金−スズ接合、高温はんだ接合が望ましい。 FIG. 3 is a schematic cross-sectional view showing a third embodiment of the semiconductor device of the present invention. This embodiment has a structure in which a metal plate 40 such as gold or copper is disposed on the metal film 30 in the semiconductor device 1 according to the first embodiment. This structure has a distance between the semiconductor integrated circuit 10 and the front surface or back surface of the semiconductor device 1, and it is not preferable from the viewpoint of productivity and economy to expose the metal film 30 on the front surface or back surface of the semiconductor device 1. For example, a metal plate made of, for example, gold, aluminum, copper, or an alloy containing these as a main component is bonded onto the metal film, and the metal plate is exposed to the front or back surface of the semiconductor device. ing.
With this configuration, as in the first embodiment, the internal electrode of the semiconductor integrated circuit 10 can be connected to the power supply or the ground line without using a long metal wiring as in the prior art. Therefore, the heat generated in the semiconductor integrated circuit can be further promoted. The metal film 30 and the metal plate 40 are preferably joined by gold-tin bonding or high-temperature solder bonding.

図４は本発明の半導体装置の第４の実施形態を示す模式的断面図である。
この実施形態は、第２の実施形態における上層金属層３０ｂの上に第３の実施形態における金属板４０を配置した構造である。
即ち、保護膜２６の上に形成させた金属膜３０ａの上にさらにポリイミド等の応力緩和膜３４を設け、その上に蒸着法、若しくはメッキ法等で例えば、金、アルミニュウム、銅又はこれらを主成分とする合金でできた金属膜３０ｂを形成させ、更にその上に金属板４０を配置した構造である。この場合も、下層の金属膜３０ａと上層の金属膜３０ｂは少なくとも１箇所で接続されている。
従って、この実施形態の半導体装置１は、第２及び第３の実施形態の備えた前記作用効果を合わせて備えている。即ち、従来のように長い金属配線を用いずに半導体集積回路１０を電源又はグランドラインに接続することにより、さらに、ヒートシンクとなる金属板４０により半導体集積回路からの放熱が一層促進されるだけでなく、応力緩和膜３４により熱応力が緩和されるため、接合部の剥離や隙間の形成が確実に防止でき、半導体装置１は破損することなく常に安定した動作を行うことができる。 FIG. 4 is a schematic cross-sectional view showing a fourth embodiment of the semiconductor device of the present invention.
In this embodiment, the metal plate 40 in the third embodiment is arranged on the upper metal layer 30b in the second embodiment.
That is, a stress relaxation film 34 such as polyimide is further provided on the metal film 30a formed on the protective film 26, and, for example, gold, aluminum, copper, or these are mainly formed by vapor deposition or plating. A metal film 30b made of an alloy as a component is formed, and a metal plate 40 is further disposed thereon. Also in this case, the lower metal film 30a and the upper metal film 30b are connected at least at one location.
Therefore, the semiconductor device 1 of this embodiment is provided with the above-described effects provided in the second and third embodiments. That is, by connecting the semiconductor integrated circuit 10 to a power source or a ground line without using a long metal wiring as in the prior art, the heat radiation from the semiconductor integrated circuit is further promoted by the metal plate 40 serving as a heat sink. In addition, since the thermal stress is relaxed by the stress relaxation film 34, peeling of the joint and formation of a gap can be reliably prevented, and the semiconductor device 1 can always perform a stable operation without being damaged.

図５は、本発明の半導体装置１の第５の実施形態を示す模式的断面図である。この実施形態は、第４の実施形態においてダイパッド１２の下側を封止用エポキシ樹脂から露出させて、ダイパッド１２が回路基板に直接接触するように構成されている。そのため、第４の実施形態の作用効果に加え、半導体集積回路１０で発生した熱はダイパッド１２を通じて回路基板に放熱することができ、その分放熱効率が向上するとの作用効果を得ることができる。   FIG. 5 is a schematic cross-sectional view showing a fifth embodiment of the semiconductor device 1 of the present invention. In this embodiment, the lower side of the die pad 12 is exposed from the sealing epoxy resin in the fourth embodiment so that the die pad 12 directly contacts the circuit board. Therefore, in addition to the operational effects of the fourth embodiment, the heat generated in the semiconductor integrated circuit 10 can be radiated to the circuit board through the die pad 12, and the operational effect of improving the heat radiation efficiency can be obtained.

図６は本発明の半導体装置１の第６の実施形態を示す模式的断面図であり、図５に示す半導体装置１におけるダイパッド１２、半導体集積回路１０、保護膜２６、第１金属膜３０ａ、応力緩和膜３４、第２の金属膜３０ｂ、金属板４０を天地逆向きに配置してワイヤー１８を介してリード１６に接続している。
この構造では、金属板が直接プリント回路基板に直接接続されるから配線抵抗を一層低減することができ、かつ、金属板の熱が直接回路基板に放熱されるとともに、ダイパッド１２も封止樹脂から露出するよう構成されているため、ダイパッド１２からの放熱も促進される。 FIG. 6 is a schematic cross-sectional view showing a sixth embodiment of the semiconductor device 1 of the present invention. The die pad 12, the semiconductor integrated circuit 10, the protective film 26, the first metal film 30a in the semiconductor device 1 shown in FIG. The stress relaxation film 34, the second metal film 30 b, and the metal plate 40 are arranged upside down and connected to the lead 16 via the wire 18.
In this structure, since the metal plate is directly connected to the printed circuit board, the wiring resistance can be further reduced, the heat of the metal plate is directly radiated to the circuit board, and the die pad 12 is also made from the sealing resin. Since it is configured to be exposed, heat dissipation from the die pad 12 is also promoted.

図７は本発明の半導体装置１の第７の実施形態を示す模式的断面図であり、図４に示す半導体装置１におけるダイパッド１２、半導体集積回路１０、保護膜２６、第１金属膜３０ａ、応力緩和膜３４、第２の金属膜３０ｂ、金属板４０を天地逆向きに配置してワイヤー１８を介してリード１６に接続している。
この構造でも、金属板が直接プリント回路基板に接続されるため、一層短距離で回路基板の電極に接続することができ、その分抵抗を低減することができる。その他の作用効果は図４に記載されたものと同様である。 FIG. 7 is a schematic cross-sectional view showing a seventh embodiment of the semiconductor device 1 of the present invention. The die pad 12, the semiconductor integrated circuit 10, the protective film 26, the first metal film 30a in the semiconductor device 1 shown in FIG. The stress relaxation film 34, the second metal film 30 b, and the metal plate 40 are arranged upside down and connected to the lead 16 via the wire 18.
Even in this structure, since the metal plate is directly connected to the printed circuit board, the metal plate can be connected to the electrode of the circuit board at a shorter distance, and the resistance can be reduced accordingly. Other functions and effects are the same as those described in FIG.

図８は本発明の半導体装置１の第８の実施形態を示す模式的断面図であり、この実施形態では、ワイヤー１８をダイパッド１２に接合し、かつダイパッド１２の下側に複数のバンプ４２を設けて、この複数のバンプ４２を介して例えばプリント回路基板の電極に接続される。その他の構成は図５に示す半導体装置１と同様であり、その作用効果もそれと同様である。
以上の各実施形態において、封止樹脂から露出させた金属膜３０又は金属板４０が金以外のときは、半導体装置１の内部を保護してその腐食防止等をするため、露出させた金属膜３０又は金属板４０の表面に金若しくははんだ或いはスズメッキを施すことが望ましい。 FIG. 8 is a schematic cross-sectional view showing an eighth embodiment of the semiconductor device 1 of the present invention. In this embodiment, the wire 18 is bonded to the die pad 12 and a plurality of bumps 42 are formed on the lower side of the die pad 12. Provided and connected to, for example, an electrode of a printed circuit board through the plurality of bumps 42. The other configuration is the same as that of the semiconductor device 1 shown in FIG. 5, and the function and effect thereof are also the same.
In each of the above embodiments, when the metal film 30 or the metal plate 40 exposed from the sealing resin is other than gold, the exposed metal film is used to protect the inside of the semiconductor device 1 and prevent its corrosion. It is desirable to apply gold, solder, or tin plating to the surface of 30 or the metal plate 40.

本発明の第１の実施形態に係る半導体装置を模式的に示す断面図である。1 is a cross-sectional view schematically showing a semiconductor device according to a first embodiment of the present invention. 本発明の第２の実施形態に係る半導体装置を模式的に示す断面図である。It is sectional drawing which shows typically the semiconductor device which concerns on the 2nd Embodiment of this invention. 本発明の第３の実施形態に係る半導体装置を模式的に示す断面図である。It is sectional drawing which shows typically the semiconductor device which concerns on the 3rd Embodiment of this invention. 本発明の第４の実施形態に係る半導体装置を模式的に示す断面図である。It is sectional drawing which shows typically the semiconductor device which concerns on the 4th Embodiment of this invention. 本発明の第５の実施形態に係る半導体装置を模式的に示す断面図である。It is sectional drawing which shows typically the semiconductor device which concerns on the 5th Embodiment of this invention. 本発明の第６の実施形態に係る半導体装置を模式的に示す断面図である。It is sectional drawing which shows typically the semiconductor device which concerns on the 6th Embodiment of this invention. 本発明の第７の実施形態に係る半導体装置を模式的に示す断面図である。It is sectional drawing which shows typically the semiconductor device which concerns on the 7th Embodiment of this invention. 本発明の第８の実施形態に係る半導体装置を模式的に示す断面図である。It is sectional drawing which shows typically the semiconductor device which concerns on the 8th Embodiment of this invention. 従来の半導体装置を模式的に示す断面図である。It is sectional drawing which shows the conventional semiconductor device typically.

符号の説明Explanation of symbols

１…半導体装置、１０…半導体集積回路、１２…ダイパッド、１４…接着剤又ははんだ、１６…リード、１８…ワイヤー、２２，２４…電極取り出し口、２６…保護膜、３０…金属膜、３２…グランド又は電源ライン、３４…応力緩和膜、４０…金属板、４２…バンプ。 DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 10 ... Semiconductor integrated circuit, 12 ... Die pad, 14 ... Adhesive or solder, 16 ... Lead, 18 ... Wire, 22, 24 ... Electrode extraction port, 26 ... Protective film, 30 ... Metal film, 32 ... Ground or power line 34... Stress relaxation film 40. Metal plate 42.

Claims (8)

半導体集積回路と、該半導体集積回路の電極端子と基板電極とを接続する導電手段を有し、樹脂封止した半導体装置において、
上記半導体集積回路上に順に積層して設けた保護膜及び金属膜を有し、該金属膜が上記保護膜の開孔部分で半導体集積回路の内部電極と接続し、かつ該金属膜を上記半導体装置の表面若しくは裏面側で上記封止樹脂から露出させたことを特徴とする半導体装置。 In a semiconductor device having a semiconductor integrated circuit and a resin-sealed semiconductor device having conductive means for connecting the electrode terminal of the semiconductor integrated circuit and a substrate electrode,
A protective film and a metal film, which are sequentially stacked on the semiconductor integrated circuit; the metal film is connected to an internal electrode of the semiconductor integrated circuit at an opening portion of the protective film; and the metal film is connected to the semiconductor A semiconductor device characterized by being exposed from the sealing resin on the front surface or back surface side of the device. 請求項１に記載された半導体装置において、
上記金属膜が応力緩和層を備えていることを特徴とする半導体装置。 The semiconductor device according to claim 1,
A semiconductor device, wherein the metal film includes a stress relaxation layer. 請求項２に記載された半導体装置において、
上記金属膜は第１及び第２の金属膜からなり、該第１及び第２の金属膜は上記応力緩和層を介在させて少なくとも１箇所で接続されており、上記第２の金属膜を半導体装置の表面、若しくは裏面側で上記封止樹脂から露出させたことを特徴とする半導体装置。 The semiconductor device according to claim 2,
The metal film is composed of first and second metal films, and the first and second metal films are connected at least at one position with the stress relaxation layer interposed therebetween, and the second metal film is connected to a semiconductor. A semiconductor device which is exposed from the sealing resin on the front surface or back surface side of the device. 請求項１に記載された半導体装置において、
上記第１の金属膜に接合された金属板を有し、かつ該金属板を上記半導体装置の表面若しくは裏面側で封止樹脂から露出させたことを特徴とする半導体装置。 The semiconductor device according to claim 1,
A semiconductor device comprising: a metal plate bonded to the first metal film, wherein the metal plate is exposed from a sealing resin on a front surface or a back surface side of the semiconductor device. 請求項２又は３に記載された半導体装置において、
上記第２の金属膜に接合された金属板を有し、かつ該金属板を上記半導体装置の表面若しくは裏面側で封止樹脂から露出させたことを特徴とする半導体装置。 The semiconductor device according to claim 2 or 3,
A semiconductor device comprising: a metal plate bonded to the second metal film, wherein the metal plate is exposed from a sealing resin on a front surface or a back surface side of the semiconductor device. 請求項１ないし５のいずれかに記載された半導体装置において、
上記第１及び第２の金属膜は金、アルミニュウム、銅又はそれを主成分とする合金からなり、
上記応力緩和層はポリイミド、エポキシ樹脂、その他のエラストマー又はプラストマーであることを特徴とする半導体装置。 The semiconductor device according to claim 1,
The first and second metal films are made of gold, aluminum, copper, or an alloy based on it,
The semiconductor device according to claim 1, wherein the stress relaxation layer is made of polyimide, epoxy resin, other elastomer or plastomer. 請求項１ないし６に記載された半導体装置において、
半導体集積回路を搭載したダイパッドを有し、該ダイパッドを半導体装置の表面若しくは裏面側で上記封止樹脂から露出させたことを特徴とする半導体装置。 The semiconductor device according to claim 1, wherein:
A semiconductor device having a die pad on which a semiconductor integrated circuit is mounted, wherein the die pad is exposed from the sealing resin on a front surface or a back surface side of the semiconductor device. 請求項１ないし７のいずれかに記載された半導体装置において、
半導体装置の表面あるいは裏面側で上記封止樹脂から露出させた金以外の金属膜又は金属板の表面にメッキ層を有することを特徴とする半導体装置。 The semiconductor device according to claim 1,
A semiconductor device having a plating layer on the surface of a metal film or metal plate other than gold exposed from the sealing resin on the front surface or back surface side of the semiconductor device.
JP2003287813A 2003-08-06 2003-08-06 Semiconductor device Withdrawn JP2005057125A (en)

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JP2003287813A JP2005057125A (en) 2003-08-06 2003-08-06 Semiconductor device
KR1020040060778A KR20050016087A (en) 2003-08-06 2004-08-02 Semiconductor device
CNB2004101047336A CN100386870C (en) 2003-08-06 2004-08-03 Semiconductor device
US10/911,509 US20050212148A1 (en) 2003-08-06 2004-08-05 Semiconductor device
TW093123585A TWI346369B (en) 2003-08-06 2004-08-06 Semiconductor device
US11/468,693 US20070120236A1 (en) 2003-08-06 2006-08-30 Semiconductor device
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005347488A (en) * 2004-06-02 2005-12-15 Fujitsu Ltd Semiconductor apparatus
US9508639B2 (en) 2014-08-06 2016-11-29 Rohm Co., Ltd. Package-in-substrate, semiconductor device and module
JP2017028131A (en) * 2015-07-23 2017-02-02 株式会社デンソー Package mounting body
JP2017034131A (en) * 2015-08-03 2017-02-09 エスアイアイ・セミコンダクタ株式会社 Semiconductor device and mounting substrate including the same
US11195803B2 (en) 2018-03-08 2021-12-07 Mitsubishi Electric Corporation Semiconductor element, semiconductor device, power conversion device, and method of manufacturing semiconductor element

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005347488A (en) * 2004-06-02 2005-12-15 Fujitsu Ltd Semiconductor apparatus
US9508639B2 (en) 2014-08-06 2016-11-29 Rohm Co., Ltd. Package-in-substrate, semiconductor device and module
JP2017028131A (en) * 2015-07-23 2017-02-02 株式会社デンソー Package mounting body
JP2017034131A (en) * 2015-08-03 2017-02-09 エスアイアイ・セミコンダクタ株式会社 Semiconductor device and mounting substrate including the same
US11195803B2 (en) 2018-03-08 2021-12-07 Mitsubishi Electric Corporation Semiconductor element, semiconductor device, power conversion device, and method of manufacturing semiconductor element

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