JPH04370943A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To flatten a formation base of a metal interconnection extended on a bonding pad for forming a cross section of the metal interconnection uniform and thereby to increase a reliability of the device by allowing a semiconductor element connected to the metal interconnection to extend as far as the downside of the bonding pad. CONSTITUTION:A semiconductor element 4, serving as a protective element for an internal circuit, constitutes a MOSFET. A drain electrode 8 is connected to a bonding pad 7 through a metal interconnection 6. Under the metal interconnection 6 and the bonding pad 7, an insulated layer 5, a diffusion layer 3 and a well layer 2 are formed solidly with a drain region D in one and the same process as the drain region D of the semiconductor element 4 is formed. Therefore, a cross section of the metal interconnection 6 from the metal interconnection 6 to the drain electrode 8 can be made uniform and there is no step in the metal interconnection 6. Since the metal interconnection 6 has no step, a cross section of the metal interconnection 6 can be formed uniform. As described above, the metal interconnection 6 has no part which has a smaller cross section than any other parts and therefore the metal interconnection is hardly fused.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device in which metal wiring is provided on a semiconductor element to connect a bonding pad and a semiconductor element via an insulating layer.

In semiconductor integrated circuit devices, internal circuits are connected to bonding pads via input protection circuits. In the input protection circuit, when a surge voltage is applied from outside the semiconductor integrated circuit, the protection element acts and discharges to the board. At that time, if a large amount of current flows from the bonding pad to the input protection circuit, the metal wiring connecting the bonding pad and the input protection circuit is thin or thin, and the cross-sectional area is blown out. For this reason,
It was necessary to ensure that the cross-sectional area of the metal wiring was sufficiently large.

0003

2. Description of the Related Art FIG. 3 is a plan view of the main parts of a conventional semiconductor integrated circuit device, and FIG. 4 is a sectional view of the main parts of the conventional semiconductor integrated circuit device. FIG. 4 shows a c-d sectional view of the plan view shown in FIG. In FIG. 3, 12 indicates a bonding pad. The bonding pad 12 is connected via a metal wiring 13 to a field effect transistor (FET) serving as a protection element.

The FET 14 has a structure in which a well layer 17 and a diffusion layer 18 are laminated on a semiconductor substrate 16, and a field oxide film 19 is formed on top of the well layer 17 and diffusion layer 18. Field oxide film 1
A drain electrode 15 , a source electrode 20 , and a gate electrode 21 are formed on the top of the electrode 9 . The drain electrode 15 and the source electrode 20 are connected to the diffusion layer 19 through a contact hole 22 formed in the field oxide film 19.

In the conventional semiconductor integrated circuit device, the bonding pad 12 is formed at a position apart from the well layer 17 and the diffusion layer 18 that constitute the FET 14, which is a protection element.

[0006]

However, in the conventional semiconductor integrated circuit device, the well layer 17 and the diffusion layer 18 are
Since it extends only to the lower part of the diffusion layer 14, a step 24 is created at the boundary 23 between the field oxide film 19 formed above the diffusion layer 18 and the diffusion layer 18. As a result, a step 25 is created in the metal wiring 13 formed above the metal wiring 13.
, since the cross-sectional area is reduced by the step 25, there is a problem that when a large current flows into the metal wire 13, the metal wire 13 is fused at a position where the cross-sectional area is small (step 25).

Furthermore, in order to obtain a sufficient cross-sectional area of the metal wiring 13, the width of the metal wiring 13 must be increased;
There was a problem that the degree of integration was reduced.

The present invention has been made in view of the above points, and the cross section of the metal wiring is made uniform to prevent the formation of portions with a small cross sectional area, so that the metal wiring is less likely to melt when a large current flows in. An object of the present invention is to provide a semiconductor integrated circuit device with improved reliability.

[0009]

[Means for Solving the Problems] The present invention provides a structure in which a semiconductor element formed by forming a semiconductor layer on a semiconductor substrate is connected to a bonding pad by a metal wiring formed on the semiconductor element via an insulating layer. In this semiconductor integrated circuit device, the semiconductor layer connected to the metal wiring extends to the bottom of the bonding pad.

0010

[Operation] By extending the semiconductor layer that constitutes the semiconductor element and is connected to the metal wiring to the bottom of the bonding pad, the base of the metal wiring and the bonding pad can be made flat. Therefore, no step is formed in the metal wiring and the bonding pad.

[0011]

[Embodiment] Fig. 1 is a plan view of essential parts of an embodiment of the present invention, Fig. 2
1 shows a sectional view of a main part of an embodiment of the present invention. In FIG. 2, 1 indicates a semiconductor substrate. A semiconductor element 4 is formed on a semiconductor substrate 1 .

The semiconductor element 4 functions as a protection element for the internal circuit and constitutes a MOS FET. Semiconductor element 4
As shown in FIG. 1, well layers 1 and 2, a diffusion layer 3, an insulating layer 5, a drain electrode 8, a source electrode 9, a gate electrode 10, etc. are laminated.

The drain electrode 8, source electrode 9, and gate electrode 10 are made of metal such as aluminum (Al), and an insulating layer 5 is formed below them. The drain electrode 8 and the source electrode 9 are connected to the diffusion layer 3 through a contact hole 11 formed in the insulating layer 5. In addition, gate electrode 1
0 is insulated from the well layer 2 by an insulating layer 5.

Drain electrode 8 is connected to bonding pad 7 via metal wiring 6 . The metal wiring 6 is made of metal such as aluminum (Al), and one end constitutes the drain electrode 8 and the other end is connected to the bonding pad 7. A wire (not shown) is connected to the bonding pad 7, and is connected to a pin for connection to an external circuit provided on the package of the semiconductor integrated circuit via the wire.

Under the metal wiring 6 and bonding pad 7, an insulating layer 5, a diffusion layer 3, and a well layer 2 are formed integrally with the drain region D in the same process as the drain region D of the semiconductor element 4.

Therefore, the a-b cross section from the metal wiring 6 to the drain electrode 8 can have a flat structure as shown in FIG. 1, and no step will occur in the metal wiring 6. Since there is no step in the metal wiring 6, the cross section of the metal wiring 6 can be formed uniformly.

[0017] In this way, since there is no portion where the cross-sectional area becomes small in the metal wiring 6, the metal wiring 6 is less likely to be blown out when a large current flows from the bonding pad 7.

Although the present embodiment has been described with reference to FETs, the present invention is not limited to this and can be applied to other semiconductor devices.

[0019]

As described above, according to the present invention, by extending the semiconductor element connected to the metal wiring to the bottom of the bonding pad, it is possible to flatten the base on which the metal wiring extends above the bonding pad. It has the advantage that the metal wiring can be formed flatly, so that the cross section of the metal wiring can be formed evenly, and the reliability of the metal wiring can be improved.

[Brief explanation of drawings]

FIG. 1 is a plan view of essential parts of an embodiment of the present invention.

FIG. 2 is a sectional view of essential parts of an embodiment of the present invention.

FIG. 3 is a plan view of main parts of a conventional example.

FIG. 4 is a sectional view of essential parts of a conventional example.

[Explanation of symbols]

1 Board 2 Well layer 3 Diffusion layer 4 Semiconductor element 5 Insulating layer 6 Metal wiring 7 Bonding pad

Claims (1)

[Claims] Claim 1: A semiconductor layer (2,
3) Semiconductor element (4) configured by forming
A bonding pad (7) is formed by a metal wiring (6) formed on the semiconductor element (4) via an insulating layer (5).
A semiconductor integrated circuit device having a structure in which the semiconductor layer (2, 3) connected on the metal wiring (6) extends to a lower part of the bonding pad (7). Integrated circuit device.