JP5263469B2 - Semiconductor device - Google Patents

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JP5263469B2
JP5263469B2 JP2007122298A JP2007122298A JP5263469B2 JP 5263469 B2 JP5263469 B2 JP 5263469B2 JP 2007122298 A JP2007122298 A JP 2007122298A JP 2007122298 A JP2007122298 A JP 2007122298A JP 5263469 B2 JP5263469 B2 JP 5263469B2
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resistance element
bump
resistance value
resistance
overlaps
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JP2008277686A (en
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康男 山▲崎▼
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Seiko Epson Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which a resistance value is not changed even if pressure is applied to the device by bonding. <P>SOLUTION: A first resistance element 20 formed by an n-type semiconductor and a second resistance element 22 formed by a p-type semiconductor are connected in series. A bump 18 is provided on an electrode 14 connected electrically to an integrated circuit 12. The first resistance element 20 includes a first overlapping portion 24 overlapping with the bump 18 and having a first resistance value. The second resistance element 22 includes a second overlapping portion 26 overlapping with the bump 18 and having a second resistance value. The first overlapping portion 24 has a property in which the first resistance value is lowered in proportion to a load applied thereto. The second overlapping portion 26 has a property in which the second resistance value is increased in proportion to a load applied thereto. The lowering rate of the first resistance value is x times the increase rate of the second resistance value. The first resistance value is 1/x times the second resistance value. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

本発明は、半導体装置に関する。   The present invention relates to a semiconductor device.

半導体装置をフェースダウンボンディングすると、バンプ下に抵抗素子がある場合、抵抗素子に圧力が加えられる（特許文献１）。ここで、抵抗素子が半導体から構成されていると、圧力によってキャリアの移動度が変化するという半導体の性質から、ボンディングの圧力によって抵抗素子の抵抗値が変動していた。その結果、設計上の抵抗値が得られないという問題があった。
特開２００３−１２４３３６号公報 When a semiconductor device is face-down bonded, if there is a resistive element under the bump, pressure is applied to the resistive element (Patent Document 1). Here, when the resistance element is made of a semiconductor, the resistance value of the resistance element fluctuates depending on the bonding pressure due to the nature of the semiconductor in which the carrier mobility changes depending on the pressure. As a result, there has been a problem that a designed resistance value cannot be obtained.
JP 2003-124336 A

本発明は、ボンディングなどによって圧力を加えても抵抗値の変動を低下させる半導体装置を提供することを目的とする。   An object of the present invention is to provide a semiconductor device that can reduce fluctuations in resistance value even when pressure is applied by bonding or the like.

（１）本発明に係る半導体装置は、
直列接続された、Ｎ形半導体からなる第１の抵抗素子及びＰ形半導体からなる第２の抵抗素子を含む集積回路が形成された半導体基板と、
前記集積回路に電気的に接続された電極と、
前記電極上に設けられたバンプと、
を有し、
前記第１の抵抗素子は、前記バンプとオーバーラップする第１のオーバーラップ部を含み、
前記第２の抵抗素子は、前記バンプとオーバーラップする第２のオーバーラップ部を含み、
前記第１の抵抗素子は、第１の層間絶縁層上に形成され、
前記第２の抵抗素子は、前記第１の層間絶縁層の上方に形成された第２の層間絶縁層上に形成される。
（２）
直列接続された、Ｎ形半導体からなる第１の抵抗素子及びＰ形半導体からなる第２の抵抗素子を含む集積回路が形成された半導体基板と、
前記集積回路に電気的に接続された電極と、
前記電極上に設けられたバンプと、
を有し、
前記第１の抵抗素子は、前記バンプとオーバーラップする第１のオーバーラップ部を含み、
前記第２の抵抗素子は、前記バンプとオーバーラップする第２のオーバーラップ部を含み、
前記第１の抵抗素子は、拡散抵抗からなり、
前記第１の抵抗素子の上に層間絶縁層が形成され、該層間絶縁層の上に前記第２の抵抗素子が形成される。
（３）
直列接続された、Ｎ形半導体からなる第１の抵抗素子及びＰ形半導体からなる第２の抵抗素子を含む集積回路が形成された半導体基板と、
前記集積回路に電気的に接続された電極と、
前記電極上に設けられた第１のバンプ及び第２のバンプと、
を有し、
前記第１の抵抗素子は、前記第１のバンプとオーバーラップする第１のオーバーラップ部を含み、
前記第２の抵抗素子は、前記第２のバンプとオーバーラップする第２のオーバーラップ部を含み、
前記第１の抵抗素子は、拡散抵抗からなる。
本発明によれば、第１及び第２の抵抗素子は、バンプとオーバーラップするので、ボンディングなどによって圧力が加えられると第１及び第２のオーバーラップ部の抵抗値は変動するが、第１のオーバーラップ部の抵抗値が低下すると、第２のオーバーラップ部の抵抗値は増加（又は、第１のオーバーラップ部の抵抗値が増加すると、第２のオーバーラップ部の抵抗値が低下）する。そのため、第１及び第２のオーバーラップ部に圧力が加えられても、第１の抵抗素子の抵抗値と第２の抵抗素子の抵抗値を合わせた合成抵抗の値の変動を低下させることができる。 ( 1 ) A semiconductor device according to the present invention includes:
A semiconductor substrate on which an integrated circuit including a first resistance element made of an N-type semiconductor and a second resistance element made of a P-type semiconductor connected in series is formed;
An electrode electrically connected to the integrated circuit;
Bumps provided on the electrodes;
Have
The first resistance element includes a first overlap portion that overlaps the bump,
The second resistance element includes a second overlap portion that overlaps the bump,
The first resistance element is formed on a first interlayer insulating layer,
The second resistance element is formed on a second interlayer insulating layer formed above the first interlayer insulating layer.
( 2 )
A semiconductor substrate on which an integrated circuit including a first resistance element made of an N-type semiconductor and a second resistance element made of a P-type semiconductor connected in series is formed;
An electrode electrically connected to the integrated circuit;
Bumps provided on the electrodes;
Have
The first resistance element includes a first overlap portion that overlaps the bump,
The second resistance element includes a second overlap portion that overlaps the bump,
The first resistance element comprises a diffused resistor,
An interlayer insulating layer is formed on the first resistive element, and the second resistive element is formed on the interlayer insulating layer.
( 3 )
A semiconductor substrate on which an integrated circuit including a first resistance element made of an N-type semiconductor and a second resistance element made of a P-type semiconductor connected in series is formed;
An electrode electrically connected to the integrated circuit;
A first bump and a second bump provided on the electrode;
Have
The first resistance element includes a first overlap portion that overlaps the first bump,
The second resistance element includes a second overlap portion that overlaps the second bump,
The first resistance element is a diffusion resistor.
According to the present invention, since the first and second resistance elements overlap with the bumps, the resistance values of the first and second overlap portions fluctuate when pressure is applied by bonding or the like. When the resistance value of the overlap portion decreases, the resistance value of the second overlap portion increases (or when the resistance value of the first overlap portion increases, the resistance value of the second overlap portion decreases) To do. Therefore, even if pressure is applied to the first and second overlap portions, it is possible to reduce fluctuations in the value of the combined resistance obtained by combining the resistance value of the first resistance element and the resistance value of the second resistance element. it can.

図１は、本発明の実施の形態に係る半導体装置を示す断面図である。図２は、図１に示す半導体装置をその表層（パッシベーション膜及びそれよりも上層）を除去して示す平面図である。図３は、図２に示す半導体装置のIII−III線断面の展開図である。   FIG. 1 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention. FIG. 2 is a plan view showing the semiconductor device shown in FIG. 1 with its surface layer (passivation film and higher layers) removed. FIG. 3 is a developed view of the semiconductor device taken along line III-III in FIG.

半導体装置は、半導体基板１０を有する。半導体基板１０は、最終製品としての半導体装置においては半導体チップであり、製造途中の中間製品においては半導体ウエハである。半導体基板１０は、集積回路１２（半導体チップには１つの集積回路１２・半導体ウエハには複数の集積回路１２）が形成されている。集積回路１２には電極１４が電気的に接続されている。詳しくは、半導体基板１０内に形成された内部配線を介して１つの集積回路１２に複数の電極１４が電気的に接続されている。半導体基板１０には、電極１４の少なくとも一部が露出する様にパッシベーション膜１６が形成されている。電極１４上には、バンプ１８が設けられている。   The semiconductor device has a semiconductor substrate 10. The semiconductor substrate 10 is a semiconductor chip in a semiconductor device as a final product, and a semiconductor wafer in an intermediate product being manufactured. An integrated circuit 12 (one integrated circuit 12 for a semiconductor chip and a plurality of integrated circuits 12 for a semiconductor wafer) is formed on the semiconductor substrate 10. An electrode 14 is electrically connected to the integrated circuit 12. Specifically, a plurality of electrodes 14 are electrically connected to one integrated circuit 12 through internal wiring formed in the semiconductor substrate 10. A passivation film 16 is formed on the semiconductor substrate 10 so that at least a part of the electrode 14 is exposed. Bumps 18 are provided on the electrodes 14.

集積回路１２は、Ｎ形半導体からなる第１の抵抗素子２０と、Ｐ形半導体からなる第２の抵抗素子２２を含む。第１及び第２の抵抗素子２０，２２は、それぞれ、ポリシリコンから構成されている。例えば、第１の抵抗素子２０はリン又は砒素などのＮ型不純物が添加されたポリシリコンであり、第２の抵抗素子２２はホウ素などのＰ型不純物が添加されたポリシリコンであってもよい。第１の絶縁膜３０上に第１及び第２の抵抗素子２０，２２が形成され、その上に第２の絶縁膜（層間絶縁膜）３２が形成されている。第２の絶縁膜３２には、第１及び第２の抵抗素子２０，２２上に、複数のコンタクトホール４１〜４４が形成され、各コンタクトホール４１〜４４には導電材料からなる埋め込み層５１〜５４が設けられている。第１の抵抗素子２０は一対の埋め込み層５１，５２の間の部分であり、第２の抵抗素子２２は、一対の埋め込み層５３，５４の間の部分である。埋め込み層５１〜５４に電気的に接続するように、第２の絶縁膜３２上に複数の配線６１〜６３が形成されている。埋め込み層５２，５３及び配線６２を介して、第１及び第２の抵抗素子２０，２２は、直列に接続されている。第１の抵抗素子２０は、配線６２とは反対側において、埋め込み層５１を介して配線６１に接続されている。第２の抵抗素子２２は、配線６２とは反対側において、埋め込み層５４を介して配線６３に接続されている。   The integrated circuit 12 includes a first resistance element 20 made of an N-type semiconductor and a second resistance element 22 made of a P-type semiconductor. Each of the first and second resistance elements 20 and 22 is made of polysilicon. For example, the first resistance element 20 may be polysilicon to which an N-type impurity such as phosphorus or arsenic is added, and the second resistance element 22 may be polysilicon to which a P-type impurity such as boron is added. . First and second resistance elements 20 and 22 are formed on the first insulating film 30, and a second insulating film (interlayer insulating film) 32 is formed thereon. In the second insulating film 32, a plurality of contact holes 41 to 44 are formed on the first and second resistance elements 20 and 22, and the buried layers 51 to 44 made of a conductive material are formed in the contact holes 41 to 44. 54 is provided. The first resistance element 20 is a portion between the pair of embedded layers 51 and 52, and the second resistance element 22 is a portion between the pair of embedded layers 53 and 54. A plurality of wirings 61 to 63 are formed on the second insulating film 32 so as to be electrically connected to the buried layers 51 to 54. The first and second resistance elements 20 and 22 are connected in series via the buried layers 52 and 53 and the wiring 62. The first resistance element 20 is connected to the wiring 61 through the buried layer 51 on the side opposite to the wiring 62. The second resistance element 22 is connected to the wiring 63 via the buried layer 54 on the side opposite to the wiring 62.

図２に示すように、第１の抵抗素子２０は、バンプ１８とオーバーラップして第１の抵抗値を有する第１のオーバーラップ部２４を含む。本実施の形態では、第１の抵抗素子２０の全体が、バンプ１８とオーバーラップする。第２の抵抗素子２２は、バンプ１８とオーバーラップして第２の抵抗値を有する第２のオーバーラップ部２６を含む。本実施の形態では、第２の抵抗素子２２の全体が、バンプ１８とオーバーラップする。   As shown in FIG. 2, the first resistance element 20 includes a first overlap portion 24 that overlaps the bump 18 and has a first resistance value. In the present embodiment, the entire first resistance element 20 overlaps the bump 18. The second resistance element 22 includes a second overlap portion 26 that overlaps the bump 18 and has a second resistance value. In the present embodiment, the entire second resistance element 22 overlaps the bump 18.

第１のオーバーラップ部２４は、受ける荷重に比例して第１の抵抗値が低下する性質を有する。第２のオーバーラップ部２６は、受ける荷重に比例して第２の抵抗値が増加する性質を有する。第１の抵抗値の低下率は、第２の抵抗値の増加率のｘ倍である。第１の抵抗値は、第２の抵抗値の１／ｘ倍である。   The first overlap portion 24 has a property that the first resistance value decreases in proportion to the load received. The second overlap portion 26 has a property that the second resistance value increases in proportion to the received load. The decreasing rate of the first resistance value is x times the increasing rate of the second resistance value. The first resistance value is 1 / x times the second resistance value.

一例として、所定の圧力を加えたとき、第１の抵抗値の低下率が１０％であり、第２の抵抗値の増加率が２．５％である場合、第１の抵抗値の低下率は、第２の抵抗値の増加率の４倍であるから、第１の抵抗値は、第２の抵抗値の１／４倍である。第１の抵抗値を２０Ωとし、第２の抵抗値を８０Ωとし、直列接続された第１及び第２のオーバーラップ部２６の合成抵抗値が１００Ωである例について説明すると、所定の圧力が加えられると、第１及び第２の抵抗値はそれぞれ次のようになる。   As an example, when a predetermined pressure is applied, when the rate of decrease in the first resistance value is 10%, and the rate of increase in the second resistance value is 2.5%, the rate of decrease in the first resistance value Is four times the increase rate of the second resistance value, the first resistance value is ¼ times the second resistance value. An example in which the first resistance value is 20Ω, the second resistance value is 80Ω, and the combined resistance value of the first and second overlap portions 26 connected in series is 100Ω will be described. Then, the first and second resistance values are as follows.

第１の抵抗値：２０Ω×（１００％−１０％）＝１８Ω
第２の抵抗値：８０Ω×（１００％＋２．５％）＝８２Ω
したがって、直列接続された第１及び第２のオーバーラップ部２６の合成抵抗値は、
１８Ω＋８２Ω＝１００Ω
であって、圧力が加えられる前と同じである。 First resistance value: 20Ω × (100% −10%) = 18Ω
Second resistance value: 80Ω × (100% + 2.5%) = 82Ω
Therefore, the combined resistance value of the first and second overlap portions 26 connected in series is
18Ω + 82Ω = 100Ω
And the same as before pressure was applied.

本実施の形態によれば、第１及び第２の抵抗素子２０，２２は、バンプ１８とオーバーラップするので、ボンディングによって圧力が加えられると抵抗値が変動するが、第１の抵抗値の低下と第２の抵抗値の増加が等しいため、結果的に抵抗値の変動がなくなる。   According to the present embodiment, since the first and second resistance elements 20 and 22 overlap the bump 18, the resistance value fluctuates when pressure is applied by bonding, but the first resistance value decreases. Since the increase in the second resistance value is equal to that in the second resistance value, the resistance value does not vary as a result.

（第１の変形例）
図４は、本発明に係る実施の形態の第１の変形例を説明する図である。第１の変形例では、第１及び第２の抵抗素子１２０，１２２は、それぞれ、半導体基板に不純物が拡散されて構成された拡散抵抗である。例えば、第１の抵抗素子１２０は、半導体基板のリン又は砒素などのＮ型不純物が添加された部分であり、第２の抵抗素子１２２は半導体基板のホウ素などのＰ型不純物が添加された部分であってもよい。第１及び第２の抵抗素子１２０，１２２は、ＬＯＣＯＳ（local oxidation of silicon）等を適用して形成した埋め込み酸化膜などの絶縁部１００によって素子分離されている。その他の構成は、上述した実施の形態で説明した内容が該当する。この変形例でも、上記実施の形態と同じ効果を達成することができる。 (First modification)
FIG. 4 is a diagram for explaining a first modification of the embodiment according to the present invention. In the first modification, each of the first and second resistance elements 120 and 122 is a diffused resistor configured by diffusing impurities in a semiconductor substrate. For example, the first resistance element 120 is a portion of the semiconductor substrate to which an N-type impurity such as phosphorus or arsenic is added, and the second resistance element 122 is a portion of the semiconductor substrate to which a P-type impurity such as boron is added. It may be. The first and second resistance elements 120 and 122 are separated from each other by an insulating portion 100 such as a buried oxide film formed by applying LOCOS (local oxidation of silicon) or the like. Other configurations correspond to the contents described in the above-described embodiment. This modification can also achieve the same effect as the above embodiment.

（第２の変形例）
図５は、本発明に係る実施の形態の第２の変形例を説明する図である。第２の変形例では、第１の抵抗素子２０の一部がバンプ２１８とオーバーラップし、第２の抵抗素子２２の一部がバンプ２１８とオーバーラップする点で上記実施の形態と異なる。この例では、第１の抵抗値とは、第１の抵抗素子２０の一部である第１のオーバーラップ部２２４の抵抗値であり、第２の抵抗値とは、第２の抵抗素子２２の一部である第２のオーバーラップ部２２６の抵抗値である。その他の構成は、上述した実施の形態で説明した内容が該当する。この変形例でも、上記実施の形態と同じ効果を達成することができる。 (Second modification)
FIG. 5 is a diagram for explaining a second modification of the embodiment according to the present invention. The second modification is different from the above embodiment in that a part of the first resistance element 20 overlaps the bump 218 and a part of the second resistance element 22 overlaps the bump 218. In this example, the first resistance value is the resistance value of the first overlap portion 224 that is a part of the first resistance element 20, and the second resistance value is the second resistance element 22. Is the resistance value of the second overlap portion 226 which is a part of. Other configurations correspond to the contents described in the above-described embodiment. This modification can also achieve the same effect as the above embodiment.

（第３の変形例）
図６及び図７は、本発明に係る実施の形態の第３の変形例を説明する図である。図６は、半導体装置をその表層（パッシベーション膜及びそれよりも上層）を除去して示す平面図であり、図７は、図６に示す半導体装置のVII−VII線断面の展開図である。 (Third Modification)
6 and 7 are diagrams illustrating a third modification of the embodiment according to the present invention. 6 is a plan view showing the semiconductor device with its surface layer (passivation film and higher layers) removed, and FIG. 7 is a developed view of a cross section taken along line VII-VII of the semiconductor device shown in FIG.

第３の変形例では、第１の絶縁膜３３０上に第１の抵抗素子３２０及び第１の配線３６１が形成され、その上に第２の絶縁膜（層間絶縁膜）３３２が形成されている。第２の絶縁膜３３２には、第１の抵抗素子３２０及び第１の配線３６０上に、複数のコンタクトホール３４１〜３４３が形成され、各コンタクトホール３４１〜３４３には導電材料からなる埋め込み層３５１〜３５３が設けられている。第１の抵抗素子３２０は一対の埋め込み層３５１，５３２の間の部分である。埋め込み層３５１〜３５３に電気的に接続するように、第２の絶縁膜３３２上に第２の抵抗素子３２２及び第２の配線３６２が形成されている。埋め込み層３５２を介して、第１及び第２の抵抗素子３２０，３２２は、直列に接続されている。同様に、埋め込み層３５１を介して、第１の抵抗素子３２０及び第２の配線３６２は直列に接続され、埋め込み層３５３を介して、第１の配線３６１及び第２の抵抗素子３２２は直列に接続されている。第２の抵抗素子３２２は、第１の抵抗素子３２０に接続された埋め込み層３５２と、第１の配線３６１に接続された埋め込み層３５３と、の間の部分である。その他の構成は、上述した実施の形態で説明した内容が該当する。   In the third modified example, the first resistance element 320 and the first wiring 361 are formed on the first insulating film 330, and the second insulating film (interlayer insulating film) 332 is formed thereon. . In the second insulating film 332, a plurality of contact holes 341 to 343 are formed on the first resistance element 320 and the first wiring 360, and a buried layer 351 made of a conductive material is formed in each contact hole 341 to 343. -353 are provided. The first resistance element 320 is a portion between the pair of buried layers 351 and 532. A second resistance element 322 and a second wiring 362 are formed on the second insulating film 332 so as to be electrically connected to the buried layers 351 to 353. The first and second resistance elements 320 and 322 are connected in series via the buried layer 352. Similarly, the first resistance element 320 and the second wiring 362 are connected in series via the embedded layer 351, and the first wiring 361 and the second resistance element 322 are connected in series via the embedded layer 353. It is connected. The second resistance element 322 is a portion between the buried layer 352 connected to the first resistance element 320 and the buried layer 353 connected to the first wiring 361. Other configurations correspond to the contents described in the above-described embodiment.

図６に示すように、第１及び第２の抵抗素子３２０，３２２は、バンプ３１８とオーバーラップするので、ボンディングによって圧力が加えられると抵抗値が変動するが、第１の抵抗値の低下と第２の抵抗値の増加が等しいため、結果的に抵抗値の変動がなくなる。   As shown in FIG. 6, since the first and second resistance elements 320 and 322 overlap with the bump 318, the resistance value fluctuates when pressure is applied by bonding, but the first resistance value decreases. Since the increase in the second resistance value is equal, the resistance value does not fluctuate as a result.

（第４の変形例）
図８は、本発明に係る実施の形態の第４の変形例を説明する図である。第４の変形例では、拡散抵抗からなる第１の抵抗素子４２０が形成され、その上に第１の絶縁膜（層間絶縁膜）４３０が形成されている。第１の絶縁膜４３０には、第１の抵抗素子４２０上に、複数のコンタクトホール４４１，４４２が形成され、各コンタクトホール４４１，４４２には導電材料からなる埋め込み層４５１，４５２が設けられている。第１の抵抗素子４２０は一対の埋め込み層４５１，４５２の間の部分である。埋め込み層４５１，４５２に電気的に接続するように、第１の絶縁膜４３０上に、ポリシリコンからなる第２の抵抗素子４２２及び第１の配線４６１が形成されている。埋め込み層４５２を介して、第１及び第２の抵抗素子４２０，４２２は、直列に接続されている。同様に、埋め込み層４５１を介して、第１の抵抗素子４２０及び第１の配線４６１は直列に接続されている。第１の抵抗素子４２０は、第１の配線４６１に接続された埋め込み層４５１と、第２の抵抗素子４２２に接続された埋め込み層４５２と、の間の部分である。第１の配線４６１及び第２の抵抗素子４２２上に、第２の絶縁膜（層間絶縁膜）４３２が形成されている。第２の絶縁膜４３２には、第２の抵抗素子４２２上に、コンタクトホール４４３が形成され、コンタクトホール４４３には導電材料からなる埋め込み層４５３が設けられている。埋め込み層４５３に電気的に接続するように、第２の絶縁膜４３２上に第２の配線４６２が形成されている。第２の抵抗素子４２２は、第１の抵抗素子４２０に接続された埋め込み層４５２と、第２の配線４６２に接続された埋め込み層４５３と、の間の部分である。その他の構成は、上述した実施の形態で説明した内容が該当する。この変形例でも、上記実施の形態と同じ効果を達成することができる。 (Fourth modification)
FIG. 8 is a diagram for explaining a fourth modification of the embodiment according to the present invention. In the fourth modification, a first resistance element 420 made of a diffused resistor is formed, and a first insulating film (interlayer insulating film) 430 is formed thereon. In the first insulating film 430, a plurality of contact holes 441 and 442 are formed on the first resistance element 420, and buried layers 451 and 452 made of a conductive material are provided in the contact holes 441 and 442, respectively. Yes. The first resistance element 420 is a portion between the pair of buried layers 451 and 452. A second resistance element 422 and a first wiring 461 made of polysilicon are formed on the first insulating film 430 so as to be electrically connected to the buried layers 451 and 452. The first and second resistance elements 420 and 422 are connected in series via the buried layer 452. Similarly, the first resistance element 420 and the first wiring 461 are connected in series via the buried layer 451. The first resistance element 420 is a portion between the buried layer 451 connected to the first wiring 461 and the buried layer 452 connected to the second resistance element 422. A second insulating film (interlayer insulating film) 432 is formed over the first wiring 461 and the second resistance element 422. In the second insulating film 432, a contact hole 443 is formed over the second resistance element 422, and a buried layer 453 made of a conductive material is provided in the contact hole 443. A second wiring 462 is formed over the second insulating film 432 so as to be electrically connected to the buried layer 453. The second resistance element 422 is a portion between the embedded layer 452 connected to the first resistance element 420 and the embedded layer 453 connected to the second wiring 462. Other configurations correspond to the contents described in the above-described embodiment. This modification can also achieve the same effect as the above embodiment.

（第５の変形例）
図９は、本発明に係る実施の形態の第５の変形例を説明する図である。第５の変形例では、第１の抵抗素子５２０の一部がバンプ５１８とオーバーラップし、第２の抵抗素子５２２の一部がバンプ５１８とオーバーラップする。その他の構成は、第３の変形例（図６参照）で説明した内容が該当する。 (Fifth modification)
FIG. 9 is a diagram for explaining a fifth modification of the embodiment according to the present invention. In the fifth modification, a part of the first resistance element 520 overlaps with the bump 518, and a part of the second resistance element 522 overlaps with the bump 518. The other configurations correspond to the contents described in the third modification (see FIG. 6).

なお、上述した各実施の形態では、一つのバンプと第１の抵抗素子（若しくは第１のオーバーラップ部）及び第２の抵抗素子（若しくは第２のオーバーラップ部）がオーバーラップする形態について説明したが、これに限られるものではない。つまり、第１のバンプと第１の抵抗素子（若しくは第１のオーバーラップ部）がオーバーラップし、第２のバンプと第２の抵抗素子（若しくは第２のオーバーラップ部）がオーバーラップしていてもよい。また、第１又は第２の抵抗素子（若しくは第１及び第２のオーバーラップ部）が複数のバンプとオーバーラップしていてもよい。   In each of the above-described embodiments, a mode in which one bump, the first resistance element (or the first overlap portion), and the second resistance element (or the second overlap portion) overlap is described. However, it is not limited to this. That is, the first bump and the first resistance element (or the first overlap portion) overlap, and the second bump and the second resistance element (or the second overlap portion) overlap. May be. Moreover, the 1st or 2nd resistive element (or 1st and 2nd overlap part) may overlap with the several bump.

本発明は、上述した実施の形態に限定されるものではなく、種々の変形が可能である。例えば、本発明は、実施の形態で説明した構成と実質的に同一の構成（例えば、機能、方法及び結果が同一の構成、あるいは目的及び結果が同一の構成）を含む。また、本発明は、実施の形態で説明した構成の本質的でない部分を置き換えた構成を含む。また、本発明は、実施の形態で説明した構成と同一の作用効果を奏する構成又は同一の目的を達成することができる構成を含む。また、本発明は、実施の形態で説明した構成に公知技術を付加した構成を含む。   The present invention is not limited to the above-described embodiments, and various modifications can be made. For example, the present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same purposes and results). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

図１は、本発明の実施の形態に係る半導体装置を示す断面図である。FIG. 1 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention. 図２は、図１に示す半導体装置をその表層（パッシベーション膜及びそれよりも上層）を除去して示す平面図である。FIG. 2 is a plan view showing the semiconductor device shown in FIG. 1 with its surface layer (passivation film and higher layers) removed. 図３は、図２に示す半導体装置のIII−III線断面の展開図である。FIG. 3 is a developed view of the semiconductor device taken along line III-III in FIG. 図４は、本発明に係る実施の形態の第１の変形例を説明する図である。FIG. 4 is a diagram for explaining a first modification of the embodiment according to the present invention. 図５は、本発明に係る実施の形態の第２の変形例を説明する図である。FIG. 5 is a diagram for explaining a second modification of the embodiment according to the present invention. 図６は、本発明に係る実施の形態の第３の変形例を説明する図である。FIG. 6 is a diagram for explaining a third modification of the embodiment according to the present invention. 図７は、本発明に係る実施の形態の第３の変形例を説明する図である。FIG. 7 is a diagram for explaining a third modification of the embodiment according to the present invention. 図８は、本発明に係る実施の形態の第４の変形例を説明する図である。FIG. 8 is a diagram for explaining a fourth modification of the embodiment according to the present invention. 図９は、本発明に係る実施の形態の第５の変形例を説明する図である。FIG. 9 is a diagram for explaining a fifth modification of the embodiment according to the present invention.

符号の説明Explanation of symbols

１０…半導体基板、 １２…集積回路、 １４…電極、 １６…パッシベーション膜、 １８…バンプ、 ２０…第１の抵抗素子、 ２２…第２の抵抗素子、 ２４…第１のオーバーラップ部、 ２６…第２のオーバーラップ部、 ３０…第１の絶縁膜、 ３２…第２の絶縁膜、 ４１…コンタクトホール、 ４２…コンタクトホール、 ４３…コンタクトホール、 ４４…コンタクトホール、 ５１…埋め込み層、 ５２…埋め込み層、 ５３…埋め込み層、 ６１…配線、 ６２…配線、 ６３…配線、 １００…絶縁部、 １２０…第１の抵抗素子、 １２２…第２の抵抗素子、 ２１８…バンプ、 ２２４…第１のオーバーラップ部、 ２２６…第２のオーバーラップ部、 ３１８…バンプ、 ３２０…第１の抵抗素子、 ３２２…第２の抵抗素子、 ３３０…第１の絶縁膜、 ３３２…第２の絶縁膜、 ３４１…コンタクトホール、 ３４２…コンタクトホール、 ３４３…コンタクトホール、 ３５１…埋め込み層、 ３５２…埋め込み層、 ３５３…埋め込み層、 ３６１…第１の配線、 ３６２…第２の配線、 ４２０…第１の抵抗素子、 ４２２…第２の抵抗素子、 ４３０…第１の絶縁膜、 ４３２…第２の絶縁膜、 ４４１…コンタクトホール、 ４４２…コンタクトホール、 ４４３…コンタクトホール、 ４５１…埋め込み層、 ４５２…埋め込み層、 ４５３…埋め込み層、 ４６１…第１の配線、 ４６２…第２の配線、 ５１８…バンプ、 ５２０…第１の抵抗素子、 ５２２…第２の抵抗素子   DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate, 12 ... Integrated circuit, 14 ... Electrode, 16 ... Passivation film, 18 ... Bump, 20 ... 1st resistance element, 22 ... 2nd resistance element, 24 ... 1st overlap part, 26 ... 2nd overlap part, 30 ... 1st insulating film, 32 ... 2nd insulating film, 41 ... Contact hole, 42 ... Contact hole, 43 ... Contact hole, 44 ... Contact hole, 51 ... Buried layer, 52 ... Embedding layer, 53... Embedding layer, 61... Wiring, 62... Wiring, 63 .. wiring, 100 .. Insulating part, 120... First resistance element, 122 ... second resistance element, 218. Overlap portion, 226, second overlap portion, 318, bump, 320, first resistance element, 322, second resistance element, 3 DESCRIPTION OF SYMBOLS 0 ... 1st insulating film, 332 ... 2nd insulating film, 341 ... Contact hole, 342 ... Contact hole, 343 ... Contact hole, 351 ... Embedded layer, 352 ... Embedded layer, 353 ... Embedded layer, 361 ... 1st 362 ... 2nd wiring, 420 ... 1st resistive element, 422 ... 2nd resistive element, 430 ... 1st insulating film, 432 ... 2nd insulating film, 441 ... Contact hole, 442 ... Contact Holes 443 ... contact holes, 451 ... buried layer, 452 ... buried layer, 453 ... buried layer, 461 ... first wiring, 462 ... second wiring, 518 ... bump, 520 ... first resistance element, 522 ... Second resistance element

Claims (3)

直列接続された、Ｎ形半導体からなる第１の抵抗素子及びＰ形半導体からなる第２の抵抗素子を含む集積回路が形成された半導体基板と、
前記集積回路に電気的に接続された電極と、
前記電極上に設けられたバンプと、
を有し、
前記第１の抵抗素子は、前記バンプとオーバーラップする第１のオーバーラップ部を含み、
前記第２の抵抗素子は、前記バンプとオーバーラップする第２のオーバーラップ部を含み、
前記第１の抵抗素子は、第１の層間絶縁層上に形成され、
前記第２の抵抗素子は、前記第１の層間絶縁層の上方に形成された第２の層間絶縁層上に形成される半導体装置。 A semiconductor substrate on which an integrated circuit including a first resistance element made of an N-type semiconductor and a second resistance element made of a P-type semiconductor connected in series is formed;
An electrode electrically connected to the integrated circuit;
Bumps provided on the electrodes;
Have
The first resistance element includes a first overlap portion that overlaps the bump,
The second resistance element includes a second overlap portion that overlaps the bump,
The first resistance element is formed on a first interlayer insulating layer,
The second resistance element is a semiconductor device formed on a second interlayer insulating layer formed above the first interlayer insulating layer. 直列接続された、Ｎ形半導体からなる第１の抵抗素子及びＰ形半導体からなる第２の抵抗素子を含む集積回路が形成された半導体基板と、
前記集積回路に電気的に接続された電極と、
前記電極上に設けられたバンプと、
を有し、
前記第１の抵抗素子は、前記バンプとオーバーラップする第１のオーバーラップ部を含み、
前記第２の抵抗素子は、前記バンプとオーバーラップする第２のオーバーラップ部を含み、
前記第１の抵抗素子は、拡散抵抗からなり、
前記第１の抵抗素子の上に層間絶縁層が形成され、該層間絶縁層の上に前記第２の抵抗素子が形成される半導体装置。 A semiconductor substrate on which an integrated circuit including a first resistance element made of an N-type semiconductor and a second resistance element made of a P-type semiconductor connected in series is formed;
An electrode electrically connected to the integrated circuit;
Bumps provided on the electrodes;
Have
The first resistance element includes a first overlap portion that overlaps the bump,
The second resistance element includes a second overlap portion that overlaps the bump,
The first resistance element comprises a diffused resistor,
A semiconductor device in which an interlayer insulating layer is formed on the first resistive element, and the second resistive element is formed on the interlayer insulating layer. 直列接続された、Ｎ形半導体からなる第１の抵抗素子及びＰ形半導体からなる第２の抵抗素子を含む集積回路が形成された半導体基板と、
前記集積回路に電気的に接続された電極と、
前記電極上に設けられた第１のバンプ及び第２のバンプと、
を有し、
前記第１の抵抗素子は、前記第１のバンプとオーバーラップする第１のオーバーラップ部を含み、
前記第２の抵抗素子は、前記第２のバンプとオーバーラップする第２のオーバーラップ部を含み、
前記第１の抵抗素子は、拡散抵抗からなる半導体装置。 A semiconductor substrate on which an integrated circuit including a first resistance element made of an N-type semiconductor and a second resistance element made of a P-type semiconductor connected in series is formed;
An electrode electrically connected to the integrated circuit;
A first bump and a second bump provided on the electrode;
Have
The first resistance element includes a first overlap portion that overlaps the first bump,
The second resistance element includes a second overlap portion that overlaps the second bump,
The first resistance element is a semiconductor device made of a diffused resistor.
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