JPS61270857A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61270857A JPS61270857A JP11160585A JP11160585A JPS61270857A JP S61270857 A JPS61270857 A JP S61270857A JP 11160585 A JP11160585 A JP 11160585A JP 11160585 A JP11160585 A JP 11160585A JP S61270857 A JPS61270857 A JP S61270857A
- Authority
- JP
- Japan
- Prior art keywords
- type diffused
- diffused layer
- semiconductor device
- resistance
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置に関し、特に半導体集積回路に形
成される抵抗の構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to the structure of a resistor formed in a semiconductor integrated circuit.
従来の半導体装置は、第２図に示すように、半導体領域
７に他の４［型の不純物を拡散した拡散層５の両端にＭ
配＊６ｔ−形成した抵抗を用いていた。この抵抗は単一
の拡散層５もしくは、導電型の同じ複数の拡散層を相互
接続して形成する構造となっていた。In the conventional semiconductor device, as shown in FIG.
*6T-formed resistors were used. This resistor has a structure in which a single diffusion layer 5 or a plurality of diffusion layers of the same conductivity type are interconnected.
前述した従来の構造では、単一の拡散層又は同じ導電型
の複数からなる拡散層により構成されているので、半導
体装置に応力（封止樹脂に加わる熱応力等）が加わった
場合、ピエゾ抵抗効果により拡散層の抵抗値が変動する
。この抵抗値変動により、集積回路の電気的特性の変動
等を生じるという欠点がある。The conventional structure described above is composed of a single diffusion layer or a plurality of diffusion layers of the same conductivity type, so when stress (such as thermal stress applied to the sealing resin) is applied to the semiconductor device, the piezoresistor The resistance value of the diffusion layer fluctuates due to this effect. This resistance value variation has the drawback of causing variations in the electrical characteristics of the integrated circuit.
本発明の半導体装置は、異なる導’−ａｔ型の拡散層を
相互接続して等価的に単一の抵抗とした抵抗素子を備え
ている。The semiconductor device of the present invention includes a resistance element in which different conductive-at type diffusion layers are interconnected to equivalently form a single resistance.
導’ｉｔ型の異なる拡散層よりなる抵抗は、抵抗値の変
動量の差があっても、その変動方向が互いに逆である。Even if there is a difference in the amount of variation in resistance value between the resistors made of diffusion layers of different conduction types, the directions of variation are opposite to each other.
この為、両抵抗を１列又は、直列に接絖し、単一の抵抗
素子を形成する事により、応力によるピエゾ抵抗効果に
よる抵抗値変動を互いに補償する事が出来る。Therefore, by connecting both resistors in a row or in series to form a single resistor element, it is possible to mutually compensate for variations in resistance value due to the piezoresistive effect due to stress.
これにより応力が加わった為、生じる抵抗値変動を防ぎ
、集積回路の電気的特性の変動を防止することができる
。Due to the stress applied, it is possible to prevent fluctuations in the resistance value and prevent fluctuations in the electrical characteristics of the integrated circuit.
次に、本発明について、図面に基づいて説明する。 Next, the present invention will be explained based on the drawings.
第１図は、本発明の一実施例の平面図である。FIG. 1 is a plan view of one embodiment of the present invention.
Ｎ型領域７にＰＭ拡散層１よりなる抵抗とＰ型拡散層２
とを形成し、このＰ散拡散層２内ＫＮ型拡散層３よりな
る抵抗を形成して、これらＰ型拡散層１よりなる抵抗と
Ｎｕ拡散層３よりなる抵抗とを紅配線６で並列接続して
単一の抵抗素子を形成している。このＰ型拡散層１より
なる抵抗とＮ型拡散層３よシなる抵抗との相互接続は直
列接続とすることもできる。A resistor consisting of a PM diffusion layer 1 and a P-type diffusion layer 2 in an N-type region 7
A resistor is formed by the KN type diffusion layer 3 in the P diffused layer 2, and the resistor made of the P type diffused layer 1 and the resistor made of the Nu diffused layer 3 are connected in parallel with the red wiring 6. to form a single resistance element. The resistor made of the P-type diffusion layer 1 and the resistor made of the N-type diffusion layer 3 may be interconnected in series.
以上、説明し友ように本発明は導電型の異なる拡散層か
らなる抵抗を並列又は直列接続する構成にする事によシ
、封止樹脂に加わる応力（主に熱応力が考えられる）が
原因の抵抗値変動を防止し、集積回路の電気的特性の変
動を防止する効果がある。As explained above, the present invention has a structure in which resistors made of diffusion layers of different conductivity types are connected in parallel or in series, thereby causing stress (mainly thought to be thermal stress) applied to the sealing resin. This has the effect of preventing fluctuations in the resistance value of the integrated circuit, and preventing fluctuations in the electrical characteristics of the integrated circuit.
第１図は、本発明の一実施例による半導体装置の平面図
、第２図は、従来の半導体装置の平面図である。
１・・・・・・Ｐ散拡散層（抵抗領域）、２・・・・・
・Ｐ散拡散層、３・・・・・・Ｎ型拡散層（抵抗領域）
、４・・・・・・Ｍ配線、５・・・・・・Ｐ散拡散層（
抵抗領域）、６・・・・・・人を配線、７・・・・・・
Ｎ型領域。FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a plan view of a conventional semiconductor device. 1...P diffusion layer (resistance region), 2...
・P diffused layer, 3...N type diffused layer (resistance region)
, 4...M wiring, 5...P diffusion layer (
Resistance area), 6... Wiring people, 7...
N-type region.
Claims (1)
素子を相互に接続した事を特徴とする半導体装置。 ２、前記相互に接続された複数の抵抗素子は等価的に単
一の抵抗を形成していることを特徴とする特許請求の範
囲第１項記載の半導体装置。[Claims] 1. A semiconductor device characterized in that a plurality of resistance elements each formed of semiconductor regions of different conductivity types are interconnected. 2. The semiconductor device according to claim 1, wherein the plurality of mutually connected resistance elements equivalently form a single resistance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11160585A JPS61270857A (en) | 1985-05-24 | 1985-05-24 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11160585A JPS61270857A (en) | 1985-05-24 | 1985-05-24 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61270857A true JPS61270857A (en) | 1986-12-01 |
Family
ID=14565579
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11160585A Pending JPS61270857A (en) | 1985-05-24 | 1985-05-24 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61270857A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008277686A (en) * | 2007-05-07 | 2008-11-13 | Seiko Epson Corp | Semiconductor device |
-
1985
- 1985-05-24 JP JP11160585A patent/JPS61270857A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008277686A (en) * | 2007-05-07 | 2008-11-13 | Seiko Epson Corp | Semiconductor device |
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