JPH02117138A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02117138A JPH02117138A JP63271190A JP27119088A JPH02117138A JP H02117138 A JPH02117138 A JP H02117138A JP 63271190 A JP63271190 A JP 63271190A JP 27119088 A JP27119088 A JP 27119088A JP H02117138 A JPH02117138 A JP H02117138A
- Authority
- JP
- Japan
- Prior art keywords
- film
- bonding pad
- surge voltage
- layer
- junction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 229910052751 metal Inorganic materials 0.000 claims abstract description 20
- 239000002184 metal Substances 0.000 claims abstract description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000009792 diffusion process Methods 0.000 claims description 13
- 230000001681 protective effect Effects 0.000 abstract description 6
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 239000003990 capacitor Substances 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract description 2
- 229920005591 polysilicon Polymers 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000016507 interphase Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体装置、詳しくは、同装置の入出力部に
関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device, and more particularly to an input/output section of the device.
従来の技術
従来の半導体装置の入出力部は、金属ボンディングパッ
ドから、コンタクト窓を通して、前記金属ボンディング
パッドと同一の金属を介して、拡散層に接続され、前記
金属ポンデイレグパッドと拡散層の接合部には、金属以
外の導電性を有した物質は存在しなかった。BACKGROUND OF THE INVENTION The input/output section of a conventional semiconductor device is connected from a metal bonding pad through a contact window to a diffusion layer through the same metal as the metal bonding pad. No conductive substance other than metal was present at the joint.
発明が解決しようとする課題
前記のような構造では、サージ電圧印加などによって大
電流がこの金属ボンディングパッドと拡散層の接合部を
流れた場合、接合部でのコンタクト抵抗、容量が小さい
ため、接合部において、大電流がコンタクト部分の金属
から拡散層を通じ半導体基板に貫通し、半導体基板と拡
散層のＰ−Ｎ接合面がダイオード特性を再現しなくなり
、導通してしまう破壊を起こしやすいという問題点を有
していた。Problems to be Solved by the Invention In the structure described above, when a large current flows through the junction between the metal bonding pad and the diffusion layer due to the application of a surge voltage, the contact resistance and capacitance at the junction are small, so the junction In this case, a large current passes through the semiconductor substrate from the metal of the contact part through the diffusion layer, and the P-N junction surface between the semiconductor substrate and the diffusion layer no longer reproduces the diode characteristics, and is prone to breakdown due to conduction. It had
本発明は上記従来の問題点を解決するもので、接合部の
サージ電圧印加などによる破壊を防止することができる
半導体装置を提供することを目的とする。The present invention solves the above-mentioned conventional problems, and aims to provide a semiconductor device that can prevent breakdown due to surge voltage application to the junction.
課題を解決するための手段
この問題点を解決するために、本発明は、半導体基板表
面に作り込まれた半導体素子部の金属ボンディングパッ
ドと、内部半導体回路に接続させるための拡散層との接
続を多結晶シリコンによっておこなう構造の半導体装置
である。Means for Solving the Problem In order to solve this problem, the present invention provides a method for connecting a metal bonding pad of a semiconductor element part formed on the surface of a semiconductor substrate and a diffusion layer for connecting to an internal semiconductor circuit. This is a semiconductor device with a structure in which this is done using polycrystalline silicon.
作用
上記の構成によって、多結晶シリコンを介する金属ボン
ディングバットと、拡散層の接合部において、金属膜と
多結晶シリコンとの接合部でのコンタクト抵抗、多結晶
シリコンのバルク抵抗、多結晶シリコンと拡散層との接
合面でのコンタクト抵抗の３者が直列に加わり、サージ
電圧印加に対する保護抵抗体となる。また、絶縁膜を介
しての接合に用いられる多結晶シリコンと半導体基板な
どとの間に存在する容量により、サージ電圧に対する保
護容量体となる。上記２点により、サージ電圧印加など
による、金属ボンディングパッドと拡散層との接合部で
の破壊を防止することが可能である。Effect With the above configuration, at the junction between the metal bonding bat via polycrystalline silicon and the diffusion layer, the contact resistance at the junction between the metal film and polycrystalline silicon, the bulk resistance of polycrystalline silicon, and the polycrystalline silicon and diffusion The three contact resistances at the junction surface with the layer are added in series and serve as a protective resistor against the application of a surge voltage. Further, the capacitance existing between the polycrystalline silicon used for bonding via the insulating film and the semiconductor substrate serves as a protective capacitor against surge voltage. Due to the above two points, it is possible to prevent destruction at the junction between the metal bonding pad and the diffusion layer due to application of a surge voltage or the like.
実施例
以下本発明の一実施例について、図面を参照しながら説
明する。第１図は入力回路部分の断面図である。図中、
１は例えばＰ型のシリコン基板、２は入力結線用のＮ型
拡散層、３は厚い絶縁膜、４はサージ対策用のＮ型の多
結晶シリコン、５は層間絶縁膜、６は金属膜で例えばア
ルミニウムである。７は保護膜、８は外部接続用ビンと
半導体内部回路とを接続する金属配線、９は金属膜と多
結晶シリコンとを接続させるためのコンタクト窓である
。第２図は半導体素子の入出力部分の平面図である。EXAMPLE An example of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of the input circuit portion. In the figure,
1 is, for example, a P-type silicon substrate, 2 is an N-type diffusion layer for input connection, 3 is a thick insulating film, 4 is N-type polycrystalline silicon for surge protection, 5 is an interlayer insulating film, and 6 is a metal film. For example, aluminum. 7 is a protective film, 8 is a metal wiring for connecting the external connection bottle and the semiconductor internal circuit, and 9 is a contact window for connecting the metal film and polycrystalline silicon. FIG. 2 is a plan view of the input/output portion of the semiconductor element.
以上の説明かられかるように、コンタクト窓９を通して
Ｎ型多結晶シリコン４に接続し、前記Ｎ型多結晶シリコ
ン４はＮ型拡散層２に接続する構造としている。As can be seen from the above description, the structure is such that the contact window 9 is connected to the N-type polycrystalline silicon 4, and the N-type polycrystalline silicon 4 is connected to the N-type diffusion layer 2.
本発明は、Ｐ型シリコン基板に限らず、Ｎ型シリコン基
板にも適用可能であり、またＭＯＳトランジスタ回路に
限らず、ダイオード、バイポーラＩＣ等、他の半導体装
置の入出力部にも適用出来ることは言うまでもない。The present invention is applicable not only to P-type silicon substrates but also to N-type silicon substrates, and is also applicable not only to MOS transistor circuits but also to input/output sections of other semiconductor devices such as diodes and bipolar ICs. Needless to say.
発明の詳細
な説明してきたように、本発明にかかる半導体装置は、
金属ボンディングパッドと、内部回路に接続する拡散層
との接合部に多結晶シリコンを用いることにより、サー
ジ電圧印加などにより、前記接合部が破壊されることを
防止する効果がある。As described in detail, the semiconductor device according to the present invention has the following features:
By using polycrystalline silicon at the junction between the metal bonding pad and the diffusion layer connected to the internal circuit, there is an effect of preventing the junction from being destroyed by application of a surge voltage or the like.
第１図は本発明にかかる半導体装置の入力端部分の断面
図、第２図は同じく平面図である。
１・・・・・・半導体基板、２・・・・・・拡散層、３
・・・・・・厚い絶縁膜、４・・・・・・多結晶シリコ
ン、５・・・・・・相間絶縁膜、６・・・・・・金属ボ
ンディングパッドと同一の金属膜、７・・・・・・保護
膜、８・・・・・・外部接続用ビンと半導体内部回路を
接続する金属配線、９・・・・・・金属膜と多結晶シリ
コンを接続するためのコンタクト窓。
代理人の氏名 弁理士 粟野重孝 ほか１名１−一一手
岑俤基Ｊ反
９− コンタクト宝−１
第２図FIG. 1 is a sectional view of an input end portion of a semiconductor device according to the present invention, and FIG. 2 is a plan view thereof. 1... Semiconductor substrate, 2... Diffusion layer, 3
... Thick insulating film, 4 ... Polycrystalline silicon, 5 ... Interphase insulating film, 6 ... Metal film same as metal bonding pad, 7. . . . Protective film, 8 . . . Metal wiring for connecting the external connection bottle and the semiconductor internal circuit, 9 . . . Contact window for connecting the metal film and polycrystalline silicon. Name of agent: Patent attorney Shigetaka Awano and 1 other person 1-11 Temasu Touki Jhan 9- Contact Takara-1 Figure 2
Claims (1)
導体素子部拡散層との接続を多結晶シリコンによってお
こなうことを特徴とする半導体装置。A semiconductor device characterized in that a metal bonding pad on the surface of a semiconductor substrate and an internal semiconductor element diffusion layer are connected by polycrystalline silicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63271190A JPH02117138A (en) | 1988-10-27 | 1988-10-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63271190A JPH02117138A (en) | 1988-10-27 | 1988-10-27 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02117138A true JPH02117138A (en) | 1990-05-01 |
Family
ID=17496604
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63271190A Pending JPH02117138A (en) | 1988-10-27 | 1988-10-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02117138A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6781238B2 (en) * | 2000-04-03 | 2004-08-24 | Nec Corporation | Semiconductor device and method of fabricating the same |
-
1988
- 1988-10-27 JP JP63271190A patent/JPH02117138A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6781238B2 (en) * | 2000-04-03 | 2004-08-24 | Nec Corporation | Semiconductor device and method of fabricating the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4811155A (en) | Protection circuit for a semiconductor integrated circuit having bipolar transistors | |
| JPS6358380B2 (en) | ||
| JPS6144454A (en) | Semiconductor device | |
| JPH0945862A (en) | Semiconductor element | |
| JPS6146986B2 (en) | ||
| JPH02117138A (en) | Semiconductor device | |
| JPS6042630B2 (en) | semiconductor equipment | |
| JPS6146989B2 (en) | ||
| JPS61129855A (en) | Semiconductor ic | |
| JPH069208B2 (en) | Semiconductor device | |
| JPS58202573A (en) | Semiconductor integrated circuit device | |
| JPS63172468A (en) | Input protective circuit | |
| JPS60120569A (en) | Input circuit | |
| JPH02214151A (en) | Input protective circuit of semiconductor device | |
| JPS645899Y2 (en) | ||
| JPS63136658A (en) | Electrostatic breakdown preventive element | |
| JPS63239972A (en) | Input protective circuit of semiconductor device | |
| JPS62122164A (en) | Input-protective circuit | |
| JPS5873160A (en) | Input protective device for semiconductor element | |
| JPH01186664A (en) | Input circuit | |
| JPH02133965A (en) | Gate protecting device | |
| JPH01304763A (en) | Semiconductor integrated circuit device | |
| JPS6290963A (en) | Mos semiconductor circuit | |
| JPH07288925A (en) | Input protection circuit | |
| JPH02219260A (en) | Noise hindrance preventing device for semiconductor device |