JPS61129855A - Semiconductor ic - Google Patents
Semiconductor icInfo
- Publication number
- JPS61129855A JPS61129855A JP25341284A JP25341284A JPS61129855A JP S61129855 A JPS61129855 A JP S61129855A JP 25341284 A JP25341284 A JP 25341284A JP 25341284 A JP25341284 A JP 25341284A JP S61129855 A JPS61129855 A JP S61129855A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- terminal
- semiconductor
- input protection
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 6
- 230000015556 catabolic process Effects 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 230000000295 complement effect Effects 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は入力保護回路を有する相補型ＭＯＳ集積回路等
の半導体集積回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit such as a complementary MOS integrated circuit having an input protection circuit.
一般にＭＯＳ）ランジスタのゲート酸化膜は、その厚さ
が０．１μｍのとき、絶縁耐圧はＩＱ［Ｖ程度しかなく
、これより薄くなるに従い耐圧は低下する。このため、
相補型ＭＯ５集積回路の入力には、ゲート酸化膜の破壊
を防止する人力保護回路が不可欠となっている。In general, when the gate oxide film of a MOS (MOS) transistor has a thickness of 0.1 μm, the withstand voltage is only about IQ[V, and as the thickness becomes thinner than this, the withstand voltage decreases. For this reason,
A human protection circuit is essential for the input of complementary MO5 integrated circuits to prevent damage to the gate oxide film.
次に入力保護回路の従来例を第２図に示す、第２図にお
いて、１０１はポンディングパッド、１０２は入力保護
抵抗、１０３．１０４は入力保護抵抗１０２とともに入
力保護回路を形成するダイオード、１０５，１０６は相
補型ＭＯ３集積回路を構成するＭｏＳトランジスタ、１
０７，１０８は電源端子である。Next, a conventional example of an input protection circuit is shown in FIG. 2. In FIG. 2, 101 is a bonding pad, 102 is an input protection resistor, 103 and 104 are diodes that form the input protection circuit together with the input protection resistor 102, and 105 , 106 are MoS transistors constituting a complementary MO3 integrated circuit, 1
07 and 108 are power supply terminals.
次にこの入力保護回路の動作について説明する。Next, the operation of this input protection circuit will be explained.
ポンディングパッド１０１に正の急峻な電圧が印加され
た場合、ダイオード１０３．１０４に生じる寄生静電容
量と人力保護抵抗１０２とで定まる時定数によりＭＯＳ
）ランジスタ１０５，１０６のゲート電極にかかる電圧
を遅延させ、この間にダイオード１０４を通して電源端
子１０７に電流を流すことによりポンディングパッド１
０１の電圧をクランプする。このことによりＭＯＳｌ−
ランジスタ１０５，１０６のゲート酸化膜に高電圧がか
かるのを防止している。また、負の急峻な電圧がポンデ
ィングパッド１０１に印加されても、同様に、ダイオー
ド１０３の順方向電流によりＭ０Ｓトランジスタｉｏｓ
、１０６のゲート電極をクランプし、ゲート酸化膜に過
電圧が印加されるのを防止している。When a steep positive voltage is applied to the bonding pad 101, the MOS
) By delaying the voltage applied to the gate electrodes of the transistors 105 and 106, and during this period, flowing current through the diode 104 to the power supply terminal 107, the bonding pad 1
Clamp the voltage of 01. This results in MOSl-
This prevents high voltage from being applied to the gate oxide films of transistors 105 and 106. Similarly, even if a steep negative voltage is applied to the bonding pad 101, the forward current of the diode 103 causes the M0S transistor ios
, 106 are clamped to prevent overvoltage from being applied to the gate oxide film.
従来の人力保護回路を構成する入力保護抵抗１０２は”
相補型ＭＯ３集積回路上で第３図に示すように構成され
ており、入力保護抵抗１０２の抵抗値は、通常、１００
〜１０００Ωに設計されている。The input protection resistor 102 that constitutes the conventional human power protection circuit is
It is configured as shown in FIG. 3 on a complementary MO3 integrated circuit, and the resistance value of the input protection resistor 102 is normally 100.
It is designed to be ~1000Ω.
入力保護抵抗１０２を実用上量も多く使われているシー
ト抵抗２０Ω／口程度のポリシリコンで形成する場合、
５０〜５０口のポリシリコン層が必要となり、チップ面
積が太き（なる原因となっていた。またできるだけ広い
面積をもたせてサージ電圧のエネルギーを分散させ発熱
を避ける必要があり、信転性よく半導体集積回路を設計
する場合、ポリシリコン層のパターン幅を２０〜３０μ
ｍ以上とる必要がある。しかしこのため、チ・ンプ面積
が拡大し、製造コストが上昇するという問題があった。When the input protection resistor 102 is formed of polysilicon with a sheet resistance of about 20Ω/hole, which is often used in practice,
A polysilicon layer of 50 to 50 holes was required, which caused the chip area to become large.Also, it was necessary to have as wide an area as possible to disperse the energy of the surge voltage and avoid heat generation, resulting in good reliability. When designing a semiconductor integrated circuit, the pattern width of the polysilicon layer should be 20 to 30 μm.
It is necessary to take more than m. However, this has resulted in problems such as an increase in the chip area and an increase in manufacturing costs.
本発明はこのような点に鑑みてなされたものであり、そ
の目的とするところは、チップ面積の増大を伴わず人力
破壊耐圧の高い半導体集積回路を提供することにある。The present invention has been made in view of these points, and an object of the present invention is to provide a semiconductor integrated circuit having a high breakdown voltage without increasing the chip area.
このような目的を達成するために本発明は、外部端子と
りだし用の電極の下に設けられた抵抗層の一方の端子を
その電極と接続し、その抵抗層の他方の端子を内部回路
に接続するようにしたものである。In order to achieve such an object, the present invention connects one terminal of a resistive layer provided under an electrode for taking out an external terminal to that electrode, and connects the other terminal of the resistive layer to an internal circuit. It was designed to do so.
本発明においては、入力保護抵抗の抵抗値が大きく半導
体集積回路の入力破壊耐圧は高くなる。In the present invention, the resistance value of the input protection resistor is large, and the input breakdown voltage of the semiconductor integrated circuit is increased.
本発明に係わる半導体集積回路の一実施例を第１図に示
す。、第１図において、ｌはポリシリコン層からなる入
力保護抵抗１０２をボンディングパッド１０１に接続す
るための端子、２は入力保護抵抗１０２を半導体集積回
路の内部回路に接続するための端子である。第１図にお
いて第３図と同一部分又は相当部分には同一符号が付し
である。An embodiment of a semiconductor integrated circuit according to the present invention is shown in FIG. In FIG. 1, 1 is a terminal for connecting the input protection resistor 102 made of a polysilicon layer to the bonding pad 101, and 2 is a terminal for connecting the input protection resistor 102 to the internal circuit of the semiconductor integrated circuit. In FIG. 1, the same or equivalent parts as in FIG. 3 are given the same reference numerals.
第１図に示すように、入力保護抵抗１０２は、ポンディ
ングパッド１０１の下に絶縁膜を介して配置されている
。通常の半導体集積回路のポンディングパッドは１００
μｍ角の大きさを持つものが使われているため、この範
囲内に入力保護抵抗を形成することは容易である。第１
図に示す入力保護抵抗は第３図に示す人力保護抵抗と同
様の働きをする。As shown in FIG. 1, the input protection resistor 102 is placed under the bonding pad 101 with an insulating film interposed therebetween. A typical semiconductor integrated circuit has 100 bonding pads.
Since a resistor having a size of μm square is used, it is easy to form an input protection resistor within this range. 1st
The input protection resistor shown in the figure functions similarly to the manual protection resistor shown in FIG.
なお本実施例においては、ポリシリコン層による人力保
護抵抗の例を示したが、入力保護抵抗としてＰ形又はＮ
形の拡散抵抗を使用することも可能である。In this example, an example of a manual protection resistor using a polysilicon layer is shown, but a P-type or N-type input protection resistor may be used.
It is also possible to use a type of diffused resistor.
以上説明したように本発明は、外部端子とりだし用の電
極の下に入力保護抵抗を設けたので、半導体集積回路の
チップ面積を増大させることなく適当な太さの抵抗を作
ることができるため、入力破壊耐圧の高い半導体集積回
路を安価に作れる効果がある。As explained above, in the present invention, since the input protection resistor is provided under the electrode for taking out the external terminal, the resistor can be made with an appropriate thickness without increasing the chip area of the semiconductor integrated circuit. This has the effect of allowing semiconductor integrated circuits with high input breakdown voltage to be manufactured at low cost.
第１図は本発明に係わる半導体集積回路の一実施例を示
す構成図、第２図は入力保護回路付相補型ＭＯＳ集積回
路の一般的回路図、第３図は従来の半導体集積回路を示
す構成図である。
１．２・・・・端子、１０１・・・・ボンディングパラ
阻 １０２・・・・入力保護抵抗。FIG. 1 is a block diagram showing an embodiment of a semiconductor integrated circuit according to the present invention, FIG. 2 is a general circuit diagram of a complementary MOS integrated circuit with an input protection circuit, and FIG. 3 is a conventional semiconductor integrated circuit. FIG. 1.2...terminal, 101...bonding para-blocker 102...input protection resistor.
Claims (1)
の電極の下に設けられた抵抗層とを備え、前記抵抗層の
一方の端子を前記電極と接続し前記抵抗層の他方の端子
を内部回路に接続したことを特徴とする半導体集積回路
。It has an electrode for taking out an external terminal provided on a substrate, and a resistance layer provided under this electrode, one terminal of the resistance layer is connected to the electrode, and the other terminal of the resistance layer is connected to the inside. A semiconductor integrated circuit characterized by being connected to a circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25341284A JPS61129855A (en) | 1984-11-28 | 1984-11-28 | Semiconductor ic |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25341284A JPS61129855A (en) | 1984-11-28 | 1984-11-28 | Semiconductor ic |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61129855A true JPS61129855A (en) | 1986-06-17 |
Family
ID=17251025
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25341284A Pending JPS61129855A (en) | 1984-11-28 | 1984-11-28 | Semiconductor ic |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61129855A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63204755A (en) * | 1987-02-20 | 1988-08-24 | Nec Corp | Semiconductor device |
| US6765773B2 (en) * | 2001-08-21 | 2004-07-20 | Koninklijke Philips Electronics N.V. | ESD protection for a CMOS output stage |
-
1984
- 1984-11-28 JP JP25341284A patent/JPS61129855A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63204755A (en) * | 1987-02-20 | 1988-08-24 | Nec Corp | Semiconductor device |
| US6765773B2 (en) * | 2001-08-21 | 2004-07-20 | Koninklijke Philips Electronics N.V. | ESD protection for a CMOS output stage |
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