JPH0373574A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To protect a chip against damage due to application of a high voltage without increasing the area of the chip by stepwisely varying the gate length of an output MOSFET. CONSTITUTION:Metal wirings 2a, 2b, 2c for forming a drain electrode are divided into three, and connected by an impurity diffused region for forming a drain region 4a. A gate region 3a is set at its gate length to L1, L2, L3 at the wirings 2a, 2b, 2c. A relation L1>L2>L3 is satisfied. In order to isolate channels of MOSFETs, a region 8 which is not doped with an n-type impurity in the case of forming source, drain regions. Thus, since an outer terminal and the ground can be made to have a continuity therebetween with a resistance of suitably large value when a high voltage is applied to the terminal, it can rapidly discharge static charge while preventing an overcurrent from flowing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit equipped with a protection function against high voltages applied to output terminals due to static electricity or the like.

[Prior Art] In the output section of a MOS type semiconductor integrated circuit, as shown in FIG. 4, the outputs MOS FET Q 1 and Q z are usually output directly without providing a special protection element. connected to the terminal. Conventionally, the protection measures have been to increase the gate length of the output MOSFET and
This is done by setting 11W to a certain prescribed value.

FIG. 5(a) is a plan view of a conventional n-channel output MO9FET. As shown in the figure, metal wirings 2g and 5 forming a train electrode and a source electrode are connected to a drain region 4a and a source region 4b provided on both sides of the gate electrode 3C via contacts 6, respectively. , and the metal wiring 5 is grounded, and the metal wiring 2g is connected to the output terminal 1. Further, the gate electrode 3C is connected to a metal wiring (not shown) via a contact 7.

Next, the basic operation of the transistor shown in FIG. 5(a) as a protection element will be explained with reference to FIG. 5(b). This device basically utilizes an npn bipolar transistor that is parasitic to an n-channel MO8FET. That is, when a high voltage is applied from an external terminal to the drain region 4a, which is an n-type diffusion layer, breakdown occurs between this region and the PE semiconductor substrate 8, and majority carriers are generated in the p-type semiconductor substrate 8. A hole is injected and drifts to the contact at GNDi.
This increases the potential of the p-type semiconductor substrate near the source region 4b, which is an n-type diffusion layer. Therefore, the junction there is biased in the forward direction, and electrons, which are minority carriers, are injected from the source region 4b, which is an n-type diffusion layer. Some of these electrons diffuse into the p-type semiconductor substrate, recombine, and disappear, but most of them flow into the nearby drain region 4a, which is an n-type diffusion layer.
The current characteristics are shown in FIG. 6, where the region marked ``■'' is a region in which current flows due to breakdown of the pn junction, and the region ``■'' is a region where the parasitic npn bipolar transistor is conductive.

As described above, when the parasitic npn bipolar transistor becomes conductive, it becomes possible to flow a large current, quickly discharging the charge that generates a high voltage from the outside, and protecting the gate oxide film from electrostatic damage.

The problem here is destruction of the pn junction due to the flow of a large current. In order to prevent this, it is necessary to reduce the amount of current per unit area at the junction, that is, the current density. As a means to achieve this,
Firstly, increasing the base width of the parasitic pnp bipolar transistor, that is, increasing the gate length of the MOSFET, and secondly, increasing the area of the junction through which current flows, that is, increasing the gate width. It will be done.

[Problems to be Solved by the Invention] In the former of the above-mentioned conventional technologies, the gate length is determined by the voltage that makes the parasitic bipolar transistor conductive, so increasing the gate length to a value greater than - is a protection function for the output MOSFET. This will result in a decrease in
In addition, in a normal state, the current supply capability of the MOSFET is reduced and normal transistor operation is inhibited.

On the other hand, if the latter is followed, the current capacity increases but a large area is required, which reduces the effect of miniaturized processes and makes it difficult to increase the density of integrated circuits.

[Means for Solving the Problems] In the semiconductor integrated circuit of the present invention, the drain electrode of the MOSFET connected to the output terminal is divided into a plurality of parts, and the gate length of the gate electrode is equal to that of the train electrode directly connected to the output terminal. The opposing portion is the longest, and the other portions facing the drain electrode are made shorter as they move away from the portion facing the train electrode directly connected to the output terminal.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view showing one embodiment of the present invention. In this figure, parts common to the conventional example shown in FIG. , 2b, and 2C, and each metal wiring is connected by an impurity diffusion region forming a drain region 4a. The gate electrode 3a has a longer gate length at each metal wiring 2a, 2b, 2c.
It is set to L2+t, . I'm here.

> L 2 > L s. In addition, 8 is each MOS
This is a region that is not doped with n-type impurities when forming source/drain regions to isolate the channel of the FET.

FIG. 2 shows an equivalent circuit diagram of the device of FIG.

R1, R3, and R5 are on-resistances when the MOSFET is turned on by a high voltage, and R, , and R4 are the resistances of the diffusion layer as wiring. These resistance values and output MOS
Currents 11, I2, and IS flowing through each part of the FET are given by the following equations, where V is the voltage applied to the external terminal.

I I= V / R1 12-(Ra +R5)・V/ ((Rz +Rs)
(R4+R5) + R2Rs I t3 =R1・V/ ((Ra +Rs) (R4
+R9) + R2R3) Here, It>12>It, (Ra, R2, Rs
)=10Ω~20Ω, (R1,R2,Rs)>(R
2. Determine the gate width and gate electrode layout so as to satisfy the condition R1).

By doing this, when a high voltage is applied to the external terminal, conduction can be established between the external terminal and the ground with an appropriately high resistance, so that static charge can be quickly removed while preventing excessive current from flowing in. can be discharged. Also, during normal operation, the resistance values of resistors R2 and R4 decrease relative to the on-resistance of the MOSFET, so
Sufficient current supply capability can be ensured by effectively using the current in the short gate length portion.

FIG. 3 is a plan view showing another embodiment of the present invention,
In this embodiment, the metal wiring 2d connected to the output terminal l
occupies the center of the drain electrode, and two metal wires 2e and 2f are arranged on each side of the drain electrode, and corresponding to the refinement of the metal wires, the gate electrode 3b has a maximum gate length at the center. ing. The metal wires constituting the drain electrode are connected by thin metal wires that function as resistors. This configuration can prevent current from concentrating on a specific contact.

[Effects of the Invention] As explained above, the present invention changes the gate length of the output MOSFET in stages.
The ET can be protected from destruction due to high voltage application caused by static electricity or the like. According to the present invention, i
It is possible to supply sufficient current during normal operation while limiting the current during coining standby.

[Brief explanation of drawings]

FIG. 1 is a plan view showing an embodiment of the present invention, and FIG. 2 is a plan view showing an embodiment of the present invention.
The equivalent circuit diagram, FIG. 3 is a plan view showing another embodiment of the present invention, FIG. 4 is a circuit diagram of the output part of the MO8 type integrated circuit, and FIG. 5(a) shows a conventional example. Plan view, Figure 5 (b
>, FIG. 6 is an explanatory diagram of the operation. 1... Output terminal, 2a-2g... Metal wiring (drain electrode), 3a-3C... Gate electrode, 4a
...Train region, 4b...Source region, 5.
...Metal wiring (source electrode), 6.7... Contact, 8... P-type semiconductor substrate.

Claims (1)

[Claims] In a semiconductor integrated circuit comprising an insulated gate field effect transistor whose drain electrode is connected to an output terminal,
The drain electrode is divided into a plurality of electrodes connected by a resistor, one of which is connected to an output terminal, and the gate electrode of the insulated gate field effect transistor has a gate length that is equal to the output terminal. A semiconductor integrated circuit characterized in that the length is longest at a portion facing the connected electrode and gradually becomes shorter as the distance from the portion increases.