JPS6284542A - Mos semiconductor circuit device - Google Patents

Abstract

PURPOSE:To obtain an input protective circuit for a MOS semiconductor circuit capable of resisting large surge voltage by connecting a bonding pad and underlay polysilicon. CONSTITUTION:An input protective circuit used in the MOS semiconductor circuit, etc. consists of an aluminum bonding pad 1, a resistor 2 by polysilicon or an impurity implanting layer, a glass-coated window 7, underlay polysilicon 8 and a junction contact 10. Structure in which the aluminum bonding pad 1 and the underlay polysilicon 8 are connected by the contact 10 is shaped. An input signal from the outside is inputted to the inside through the underlay polysilicon layer by the junction contact 10. According to such structure, the bonding pad section to which surge energy is easy to concentrate can be constituted of the polysilicon having a large area without increasing the area of a chip, thus improving surge breakdown withstanding voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an input protection circuit for preventing destruction of a MOS semiconductor circuit.

[Prior Art] In a MOS semiconductor circuit, the gate insulating film is formed of a very thin oxide film of about several hundred amperes, so if an excessive surge voltage is applied from the outside, this gate The oxide film may cause dielectric breakdown, resulting in a fatal failure.

Therefore, in the MO3 semiconductor circuit, damage caused by surge voltage at its input terminal? Most are equipped with an input protection circuit to prevent this.

An example of a conventional input protection circuit is the one shown in FIG. In the figure, la and lb are input terminals of the MOS semiconductor circuit, 2a and 2b are resistors made of an impurity implanted layer or polysilicon, 3 is a diode for absorbing surges to the power supply side, and 4 is a surge absorber to the ground side. Diodes 5a and 5b are MOS transistors that receive signals from input terminals.

Regarding the vicinity of la, 2a or lb, 2b in Figure 3,
FIG. 2 shows the layout pattern of an actual MOS semiconductor circuit. In the figure, 1 is an aluminum bonding pad, 2t/'i polysilicon or impurity implantation waste, 7 is a glass coated window, 8 is an underlying polysilicon, and 9 is a junction contact between aluminum and the resistor 2.

Next, the operation will be explained. The input protection circuit shown in FIG. 3(a) is an input protection circuit often used in CMO3 semiconductor circuits. The surge voltage applied to the input terminal 1a is applied to the gate of the transistor 5a according to a time constant determined by the resistor 2a, the gate capacitance of the transistor 5a, the stray capacitance, and other capacitances.

The diode 3.4 absorbs the surge voltage before the voltage applied to the gate reaches the gate dielectric breakdown voltage, and serves as a clamp diode to prevent a voltage higher than the breakdown voltage from being applied to the gate.

The diode 3Fi functions as a clamp diode for positive surge voltages, and the diode 4 functions as a clamp diode for negative surge voltages.

Next, the input protection circuit shown in FIG. 3(b) is an input protection circuit used in a single channel MO3 semiconductor circuit or the like. The operation is almost the same as in Fig. 1(a), but
In this case, the transistor 6, which is always off, serves as a clamp against surge voltages of both positive and negative polarities.

[Problems to be solved by the invention] The conventional input protection circuit has the above configuration.
The resistor used is a P+ or N'' layer formed by impurity implantation, or polysilicon. When a P+ or riN layer is used, an excessive surge voltage may cause the impurity implantation layer to be in contact with the semiconductor substrate. There has been a problem in that the PN junction formed in this case is easily destroyed.

Furthermore, when polysilicon is used as a resistor, there is a problem that the polysilicon melts due to surge voltage due to poor heat dissipation.

It is an object of the present invention to eliminate the drawbacks of the conventional input protection circuits as described above and to provide an input protection circuit that can withstand larger surge voltages.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, l, 2.7.8.91d Same as the iQ diagram,
These are aluminum bonding pads, resistors with polysilicon or impurity implant layers, glass coated windows, underlying polysilicon, and bonding contacts. Reference numeral 10 constitutes a requirement of the present invention, and serves as a bonding contact that connects the aluminum bonding pad 1 and the deionized polysilicon 8. By adopting such a structure, the energy of the surge voltage applied from the outside is not concentrated only in the resistor 2, but is also divided into the underlying polysilicon 8, making it difficult for the resistor 2 to break or melt. .

Next, another embodiment of the present invention is shown in FIG. In this case, an input signal from the outside is inputted into the interior through the junction contactor 10 via the underlying polysilicon layer. Generally, surge voltage energy tends to concentrate near the aluminum bonding pad, but by adopting this structure, the areas where surge energy tends to concentrate can be constructed using large area polysilicon without increasing the chip area. This can improve surge breakdown resistance.

[Fruit of the invention 1 As described above, according to the present invention, the energy of the surge voltage from the outside can be dispersed by connecting the aluminum positive dig band and the underlying polysilicon, without increasing the chip area. , an input protection circuit with high breakdown resistance can be obtained.

[Brief explanation of drawings]

FIG. 1 shows an embodiment of the input protection circuit of the present invention, FIG. 2 shows another embodiment of the invention, FIG. 3 shows a conventional input protection circuit, and FIG. 4 shows its layout. 1%la, lb is aluminum bonding pad, 2.2
a. 2b is a resistor, 3.4 is a diode for absorbing S'', 5a
, 5b is a transistor, 6Ir1 off transistor, 7
Glass coated window, 8Fi underlay polysilicon, 9.10
is a bonded contact.

Claims (1)

[Claims] It has an aluminum bonding pad for connecting signals inside the semiconductor to the outside, and an underlying polysilicon layer disposed below the bonding pad with an insulating film interposed therebetween, and the bonding pad and the underlying polysilicon layer are connected to at least one place. A MOS semiconductor circuit device characterized by being connected in the above manner.