JPS5873160A - Input protective device for semiconductor element - Google Patents
Input protective device for semiconductor elementInfo
- Publication number
- JPS5873160A JPS5873160A JP56171114A JP17111481A JPS5873160A JP S5873160 A JPS5873160 A JP S5873160A JP 56171114 A JP56171114 A JP 56171114A JP 17111481 A JP17111481 A JP 17111481A JP S5873160 A JPS5873160 A JP S5873160A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- input
- resistance layer
- terminal
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 230000001681 protective effect Effects 0.000 title claims 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 206010011224 Cough Diseases 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 abstract description 8
- 229910052751 metal Inorganic materials 0.000 abstract description 6
- 239000002184 metal Substances 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 241000394600 Viola vallicola Species 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Amplifiers (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Protection Of Static Devices (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は接続される半導体素子の一作一をなくした半導
体素子用入力保−装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an input protection device for semiconductor devices that eliminates the need for each semiconductor device to be connected.
従来の半導体素子用入力保護装置として、例えば、第１
図０）に示すものがあり、Ｎａ１ｌシリコン基板１１に
Ｎ＋ ｍ拡散層ｘｉａＸ数キロオームの抵抗値を有する
Ｐ型拡散抵抗層２、およびＰウェル１２が形成されてお
シ、Ｐウェル１２にＮ４拡散層１２ｍおよびｐ ＋ ４
拡散層１２ｍが形成されている。Ｎ型シリコン基板１１
の表面に各拡畝層に逼じるコンタクトホールを有するシ
リコン酸化物ＪｍｌＯが形成されており、該コンタノド
ホールを介して所定の電気的成就を行うアルミニウム蒸
涜による金属配線９が設けられて（、・する。この金属
配線９は、入力端子１と、ＶＤＤ端子６と、■５、−子
７と、ゲート端子８へ接続され、その等薗回路は第１図
（ロ）に示すように１なシ、入力端子１とＹａｐ ４子
６の間にダイオード３、Ｐ型拡故抵抗層２の出力端子と
ＶＤＤ端子６０間にダイオード４、およびＰｆｉ拡赦抵
抗層２の出力端子とＶＢ２ ｍ子７の間にダイオード５
が形成される。As a conventional input protection device for semiconductor devices, for example, the first
There is a type shown in Fig. 0), in which a P-type diffused resistance layer 2 having a resistance value of several kilohms, an N + m diffusion layer xia layer 12m and p + 4
A diffusion layer 12m is formed. N-type silicon substrate 11
A silicon oxide JmlO having contact holes extending to each expanded ridge layer is formed on the surface of the silicon oxide JmlO, and a metal wiring 9 made of aluminum evaporation is provided to achieve a predetermined electrical effect through the contact holes. (,・.This metal wiring 9 is connected to the input terminal 1, the VDD terminal 6, the - terminal 7, and the gate terminal 8, and the circuit is as shown in Figure 1 (b). 1, a diode 3 is connected between the input terminal 1 and the Yap 4 element 6, a diode 4 is connected between the output terminal of the P-type extended resistance layer 2 and the VDD terminal 60, and a diode 4 is connected between the output terminal of the Pfi expanded resistance layer 2 and VB2. Diode 5 between m-child 7
is formed.
以上の構成において、入力端子１に与える入力−圧を制
御することによシゲート端子８に接絖されるＦＥＴ （
図示せず）のケート−圧ｍｌＪ ｄ を行ｈ１ ドレイ
ン′−流を制御することができる。In the above configuration, the FET (
The drain flow can be controlled by applying a drain pressure mlJ d (not shown).
また、入力端子１とゲート端子８の間に数計−オームの
拡散抵抗層２を形成するとともにクランプ用のダイオー
ド３，４．５を設ｖｆたため、入力端子１に異常′磁圧
が加えられても、半導体素子、例えば、ＦＥＴのゲート
、ノース間の絶縁破壊を防ぐことができる。In addition, a diffusion resistance layer 2 of several ohms was formed between the input terminal 1 and the gate terminal 8, and clamping diodes 3 and 4.5 were installed, so that an abnormal magnetic pressure was applied to the input terminal 1. However, dielectric breakdown between the gate and the north of a semiconductor element, for example, an FET, can be prevented.
しかし、従来の半導体Ａ子用入力保−ＡＩＭにあっては
入力端子１とゲート端子８の間に設けられた拡散抵抗
層２の抵抗層がりイロオーム＠度で低く、また、入力端
子１とＶ。ｌ、端子６がダイオード３で結合されてｈる
ため、例えば、４００〜５００ボルトの一周波ブ”−７
′祇圧〃ｉ元生する車両用として使用すると、高周波サ
ーフ−圧がｖＤＤ端子６、ｖ０端子７のライ／をｊ１シ
たり、あるいはＰ型拡Ｗｋ抵抗層２０ＰＮ接合を介する
ことによりて接続された半纏体水子に人力し、該半導体
素子を誤作動させる恐れがある。However, in the conventional input protection AIM for semiconductor A, the resistance layer of the diffused resistance layer 2 provided between the input terminal 1 and the gate terminal 8 is low in ohms, and the resistance between the input terminal 1 and the V . Since terminal 6 is coupled with diode 3, for example, a 400-500 volt single frequency waveform "-7"
When used in a vehicle that generates high pressure, the high frequency surf pressure is connected by crossing the lines of the vDD terminal 6 and v0 terminal 7, or by connecting the P-type expanded Wk resistance layer 20 to the PN junction. There is a risk that the semiconductor device may malfunction due to manual force applied to the semi-integrated body of water.
本発明は、上記に―みてなされたものでりり、接続され
る半導体素子が高周波サージによって誤作動するのを防
ぐため、クランプ用ダイオードの大力側に５０〜５００
キロオームの高抵抗ｊ−Ｔ設けた半導体水子用人力保護
装置を提供するものでめる。The present invention has been made in view of the above, and in order to prevent connected semiconductor elements from malfunctioning due to high frequency surges, a voltage of 50 to 500 is applied to the high-power side of the clamp diode.
The present invention provides a personal protection device for semiconductor water droplets equipped with a high resistance j-T of kilohms.
以下、本発明による半纏本素子用入力保−装置を詳細に
説明する。Hereinafter, the input retaining device for a half-bound book element according to the present invention will be explained in detail.
第２Ｊ（イ）は本発明の一実施例を示し、第１図（イ）
と同一の部分は同一の引用数字で示したのでｍ−すω説
明は省略するが、ノリコン酸化物層１０上に５０〜５０
０ギロオームの抵抗値を有す４・多結晶シリコン抵抗層
１４が設けられ、多結晶シリコン抵抗層ｄ １４がＰ型
拡散抵抗ノー２へ接続される金属配−９と入力端子１へ
接続され−るｆＮＩ４配磯９の両省と接続するコンタク
トホールの部分を除いてシリコン酸化物ノー１３によっ
て絶縁されている。／リコン酸化物層１３は多結晶シリ
コン抵抗層１１４の熱酸化あるいはＣＶＤにより形成さ
れる。2J(a) shows an embodiment of the present invention, and FIG. 1(a)
Since the same parts are indicated by the same quotation numerals, the explanation is omitted, but 50 to 50
A polycrystalline silicon resistance layer 14 having a resistance value of 0 gyrohms is provided, and the polycrystalline silicon resistance layer d14 is connected to the metal trace 9 connected to the P-type diffused resistor 2 and to the input terminal 1. It is insulated by a silicon oxide layer 13 except for the contact hole portions that connect with both sides of the fNI4 interconnection 9. /recon oxide layer 13 is formed by thermal oxidation or CVD of polycrystalline silicon resistance layer 114.
第２図（口〕は多結晶シリコン抵抗層１４を示し、入力
端子１へ接続される金属配置９（第２図（イ））よ構成
る入力バッド１６とシリコ／酸化物ｌ−１３（第２図（
イ））のコンタクトホール１３ａ ｋ介して接続され、
多結晶シリコン抵抗増１４の入力熾ａに電界果中が発生
して絶縁破壊しないようにするため、入力端ａの幅が拡
大さくしている。多結晶シリコン抵抗層１４は、７１ζ
ロンまたはリンをＩ Ｑ”／ｃｍ２機にイオン注入する
ことによシ５００〜１０００オーム／口のノート抵ｖＬ
憧を得ることができ、厚さを３５００１としｌことざ１
１＠を５ｐｍ、長さを２５０〜２５００μｍにすること
によって５０−７５００ヤロオームの抵抗値を潜ること
ができる。2(a) shows the polycrystalline silicon resistance layer 14, the input pad 16 consisting of the metal arrangement 9 (FIG. 2(a)) connected to the input terminal 1, and the silicon/oxide l-13 ( Figure 2 (
b)) are connected through the contact holes 13a k,
In order to prevent an electric field from occurring at the input terminal a of the polycrystalline silicon resistor 14 and causing dielectric breakdown, the width of the input terminal a is increased. The polycrystalline silicon resistance layer 14 is 71ζ
Note resistance vL of 500-1000 ohm/mouth can be achieved by ion implantation of ion or phosphorus into IQ”/cm2 machine.
You can get your dreams, and the thickness is 35001.Proverb 1
By setting 1@ to 5 pm and the length to 250 to 2,500 μm, a resistance value of 50 to 7,500 ohms can be achieved.
第２図ｅ）は第２図（イ）の等価回路を示し、クランプ
用ダイオード３と、拡散抵抗Ｊｌｌｉ ２の人力−に５
０〜５００キロオームの抵抗１４が設けられている構成
において、第１図（イ）の等価回路と相違している。Figure 2e) shows the equivalent circuit of Figure 2(a), with a clamping diode 3, a diffusion resistor Jlli 2, and 5
The structure differs from the equivalent circuit in FIG. 1(a) in that a resistor 14 of 0 to 500 kilohms is provided.
第３図（イ）は、以上説明した４発明の半導体累子用入
力保ａ装置２０を、アルミニウムゲートＣＭＯ８ＦＥＴ
よ構成る２段インノく一夕２１の誤作−を防ぐために通
用した実施列を示したものでおり、入力保護装置２００
Å力端子１１ｖＤＤ端子６、■１１□端子７、ゲート端
子８は第２１印。FIG. 3(a) shows an input protection device 20 for a semiconductor resistor according to the four inventions described above, which is an aluminum gate CMO8FET.
This shows an implementation sequence that has been used to prevent errors in the input protection device 200.
The power terminal 11vDD terminal 6, ■11□terminal 7, and gate terminal 8 are the 21st marks.
ＰＭと同一の引用数子ご示し、第３図（ロ）は、入力沫
諌装置２０の入力端子１に一周波す−ジｖｉｎを入力し
たとき漏れ通路ｖＬを介して２段イノ・；−夕２１の出
力端子１７より漏洩する高周波サージＶ。ｕｔを（１４
１１定した結果を示す。この測定における尚周波サージ
ｖｊ、＋は、周波数１メガヘルツ、−圧±３００ボルト
であり、入力保ｌｉ！ｉｊ脱瀘２０の多結晶７リコ／抵
抗層１４の抵抗値を１キロオームから１００キロオーム
に変え、出力端子１７の一周波す−ジＶ。ｕｔ （漏れ
電圧）を測定した。Referring to the same quotation as PM, Fig. 3 (b) shows that when one frequency is input to the input terminal 1 of the input tampering device 20, the second-stage inno; High frequency surge V leaks from the output terminal 17 of 21. ut (14
11 The results are shown below. The frequency surge vj,+ in this measurement is 1 MHz frequency, -voltage ±300 volts, and the input voltage li! By changing the resistance value of the polycrystalline 7-liquid/resistance layer 14 of the ij removal 20 from 1 kilohm to 100 kilohm, the one-frequency waveform of the output terminal 17 is set. ut (leakage voltage) was measured.
漏れ制周波サージＶ。ｕｔが１ボルト以下であれば、２
ボイ／バータ２１の誤作動がなく、そのためＫ、＋１ｓ
Ｊｒ＆シリコン抵抗層１４の抵抗値を５０ヤロオ一ム以
上にするのが望ましい。Leakage control frequency surge V. If ut is less than 1 volt, then 2
There is no malfunction of the VOI/verter 21, so K, +1s
It is desirable that the resistance value of the Jr&silicon resistance layer 14 be 50 mm or more.
向、多結晶シリコン抵抗層１４の抵抗値が５０（Ｊキロ
オーム以上になると、入カッくツド１６（第２図（ロ）
）の下のシリコン酸化物ノーの谷菫に基いて高周波！ノ
′−ジＶｌｎがノリコン基板１１（＠２図（イ））へ流
れるため好ましくない。従って、多結晶シリコン抵抗層
１４の抵抗値は５０〜５００キロオームが２１ｉ尚であ
シ、ま九、拡散抵抗層２（第２図（イ））の分布容量か
ら矩まる時定数が入゛力高周波サージＶｌｎの振動周期
よシ大になると漏れ高周波サージＶ。鱈の振ｌ１ａｔｌ
−小さくするのによシ一層効果的でおる。If the resistance value of the polycrystalline silicon resistance layer 14 exceeds 50 (J kilohms), the input capacitor 16 (see Fig. 2 (b)
) based on the valley violet of silicon oxide no under the high frequency! This is not preferable because the nozzle Vln flows to the silicon substrate 11 (@Fig. 2 (a)). Therefore, the resistance value of the polycrystalline silicon resistance layer 14 must be 50 to 500 kilohms. When the vibration period of the high frequency surge Vln becomes larger, the high frequency surge V leaks. Cod roll l1atl
- It is more effective as it is made smaller.
また、本発明による入力保護装置はンリコンゲー） ０
ＭＯ８にも同様に適用することができるのはもちろんで
あるし、また、ＮＭＯ８、ＰＭＯ＆の別を問わない。In addition, the input protection device according to the present invention is compatible with
Of course, it can be similarly applied to MO8, and it does not matter whether it is NMO8 or PMO&.
以上説明した通シ、本発明による半導体素子用入力保−
装置によれば、クランノ用ダイオードの入力側に５０〜
５００ギロオームの高抵抗層を設けたため、半導体素子
が一周波サージによって誤作動するのを防ぐことができ
る。In general, the input protection for semiconductor devices according to the present invention has been explained above.
According to the device, 50~ on the input side of the crano diode.
The provision of a high resistance layer of 500 gigrohms prevents the semiconductor device from malfunctioning due to one-frequency surges.
第１図（イ）、（ロ）は従来の半導体素子用入力保−装
置を示し、（イ）は断面図、（ロ）は（イ）の等価回路
図。
粛２図げ昌（ロ）、０は本発明の第１の実施例を示し、
（イ）は断面図、（ロ）は（イ）の入力パッドおよび多
結晶シリコン抵抗ノーを示す平面図、ｆうは（イ）の等
価回路図。第３図ピッ、（ロ）ノは本発明の適用例を示
し、（イ）は回路図、（ロ）は（イ）の漏れ＾周波サー
ジの０４１Ｊ建結呆金示す特性図。
符号の説明
１・・・入力端子 ２・・・拡散抵抗層３．４
．５・・・クラン／用ダ偵−ド６・・・”ＤＤ端子７
、Ｖ、、−子 ８・・・ゲート端子９・・・金
属配線 １０・・・７リコン酸化物層１１・
・・シリコン基板 １２・・・Ｐウェル１３・・・シ
リコン酸化 １４・・・多結晶シリコン抵抗層１６・
・・入力パッド １７・・・出方端子２０ ・入力
保護装置 ２１・・・２段インバータ第１図
（イ）
（ロ）
第２図
（イ）
（０）FIGS. 1(a) and 1(b) show a conventional input protection device for semiconductor devices, in which (a) is a sectional view and (b) is an equivalent circuit diagram of (a). 2 shows the first embodiment of the present invention,
(a) is a sectional view, (b) is a plan view showing the input pad and polycrystalline silicon resistor of (a), and f is an equivalent circuit diagram of (a). FIG. 3 shows an application example of the present invention, (a) is a circuit diagram, and (b) is a characteristic diagram showing the leakage frequency surge of (a). Explanation of symbols 1... Input terminal 2... Diffused resistance layer 3.4
．． 5... Clan/use data code 6..."DD terminal 7
, V,, - child 8... Gate terminal 9... Metal wiring 10... 7 Silicon oxide layer 11.
...Silicon substrate 12...P well 13...Silicon oxide 14...Polycrystalline silicon resistance layer 16...
... Input pad 17... Output terminal 20 - Input protection device 21... Two-stage inverter Figure 1 (A) (B) Figure 2 (A) (0)
Claims (2)
導体素子のゲート絶縁耐圧よシ低い耐圧を有した保護用
ダイオードを備えた装置において、高周波サージが入力
したとき咳高周波サージを前記半導体素子が誤作−しな
いレベルまで誠糞させる高抵抗層を前記保護用ダイオー
ドの入力側に設は九ことを特徴とする半導体素子用入力
保護装置。(1) In a device including a semiconductor element formed on a semiconductor substrate and a protective diode having a withstand voltage lower than the gate dielectric strength voltage of the semiconductor element, when a high frequency surge is input, the semiconductor element absorbs the cough high frequency surge. 1. An input protection device for a semiconductor device, characterized in that a high resistance layer is provided on the input side of the protection diode to ensure integrity to a level that prevents errors.
、５０〜５００キロオームの嬬抗臘を有する構成の特許
請求の範囲第１項ｍｌ載の半導体素子用入力保護装置Ｉ
ｔ。(2) The input protection device I for a semiconductor device according to claim 1, wherein the high resistance layer is formed similar to a polycrystalline silicon layer and has a resistance of 50 to 500 kilohms.
t.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56171114A JPS5873160A (en) | 1981-10-26 | 1981-10-26 | Input protective device for semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56171114A JPS5873160A (en) | 1981-10-26 | 1981-10-26 | Input protective device for semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5873160A true JPS5873160A (en) | 1983-05-02 |
Family
ID=15917225
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56171114A Pending JPS5873160A (en) | 1981-10-26 | 1981-10-26 | Input protective device for semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5873160A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5883161U (en) * | 1981-11-30 | 1983-06-06 | 三洋電機株式会社 | Electrostatic damage prevention structure in semiconductor devices |
| JPS60152069A (en) * | 1984-01-20 | 1985-08-10 | Toshiba Corp | Semiconductor device |
| US4937639A (en) * | 1987-10-16 | 1990-06-26 | Nissan Motor Company, Limited | Input protector device for semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54101283A (en) * | 1978-01-27 | 1979-08-09 | Hitachi Ltd | Gate protective device |
-
1981
- 1981-10-26 JP JP56171114A patent/JPS5873160A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54101283A (en) * | 1978-01-27 | 1979-08-09 | Hitachi Ltd | Gate protective device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5883161U (en) * | 1981-11-30 | 1983-06-06 | 三洋電機株式会社 | Electrostatic damage prevention structure in semiconductor devices |
| JPS60152069A (en) * | 1984-01-20 | 1985-08-10 | Toshiba Corp | Semiconductor device |
| US4937639A (en) * | 1987-10-16 | 1990-06-26 | Nissan Motor Company, Limited | Input protector device for semiconductor device |
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