JPS60152069A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60152069A JPS60152069A JP795684A JP795684A JPS60152069A JP S60152069 A JPS60152069 A JP S60152069A JP 795684 A JP795684 A JP 795684A JP 795684 A JP795684 A JP 795684A JP S60152069 A JPS60152069 A JP S60152069A
- Authority
- JP
- Japan
- Prior art keywords
- region
- source
- layer
- electrode
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 6
- 239000012535 impurity Substances 0.000 claims description 13
- 238000000605 extraction Methods 0.000 claims description 8
- 238000002955 isolation Methods 0.000 abstract description 6
- 238000007493 shaping process Methods 0.000 abstract 2
- 239000006185 dispersion Substances 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 〔発明の技術分野〕 本発明は、半導体装置に関する。[Detailed description of the invention] [Technical field of invention] The present invention relates to a semiconductor device.
従来、インピーダンス変換等に使用される接合型電界効
果トランジスタからなる半導体装置として、例えば第１
図に示す構造のものがある。Conventionally, as a semiconductor device consisting of a junction field effect transistor used for impedance conversion etc., for example, a first
There is a structure shown in the figure.
図中１は、Ｐ型の半導体基板２上に積層されたエピタキ
シャル層である。エピタキシャル層１の所定領域には、
半導体基板２に達する拡散深さでＰ型の高濃度不純物領
域からなるアイソレーション層３が形成されている。エ
ピタキシャル層１には、このアイソレージ、ン層３で仕
切られた素子領域４と抵抗層領域５が設けられている。1 in the figure is an epitaxial layer laminated on a P-type semiconductor substrate 2. In FIG. In a predetermined region of the epitaxial layer 1,
An isolation layer 3 made of a P-type high concentration impurity region is formed with a diffusion depth reaching the semiconductor substrate 2 . The epitaxial layer 1 is provided with an element region 4 and a resistance layer region 5 separated by the isolation layer 3.
素子領域には、Ｎ型の高ｅ度不純物からなるソース領域
６及びドレイン領域７が所定間隔で設けられている。ソ
ース領域６とドレイン領域７間の素子領域４には、Ｐ型
の高濃度不純物領域８が形成されている。これらの不純
物領域３，６・・・８ｔ−含むエピタキシャル層１の主
面には、絶縁膜９が形成されている。絶縁＃９０所定領
域には、ソース領域６、ドレイン領域７、高濃度不純物
領域８、ソース抵抗′層領域５に通じるコンタクトホー
ル６ａ、７ａ、８ａ、５ｔ。In the element region, a source region 6 and a drain region 7 made of N-type high-e impurity are provided at a predetermined interval. A P-type high concentration impurity region 8 is formed in the element region 4 between the source region 6 and the drain region 7 . An insulating film 9 is formed on the main surface of the epitaxial layer 1 including these impurity regions 3, 6...8t-. Contact holes 6a, 7a, 8a, and 5t communicating with the source region 6, the drain region 7, the high concentration impurity region 8, and the source resistor' layer region 5 are provided in the predetermined regions of the insulation #90.
５ｂが夫々開口されている。絶縁膜９上には、コンタク
トホール６１．５ａ’ｉ介してソース領域６とソース抵
抗層領域５に接続する取出配線層１０、コンタクトホー
ル７ａを介してドレイン領域７に接続するドレイン取出
電極１１、コンタクトホール８ｔａｆ介して高濃度不純
物領域８に接続するダート電極１２、コンタクトホール
５ｂｆ介してソース抵抗層領域５に接続するソース取出
電ＶｊＴ、１３が夫々形成されている。5b are each opened. On the insulating film 9, a lead-out wiring layer 10 is connected to the source region 6 and the source resistance layer region 5 through the contact hole 61.5a'i, a drain lead-out electrode 11 is connected to the drain region 7 through the contact hole 7a, A dirt electrode 12 connected to the high concentration impurity region 8 through a contact hole 8taf, and a source extraction voltage VjT, 13 connected to the source resistance layer region 5 through a contact hole 5bf are formed, respectively.
このように構成された半導体装置１５では、ソース抵抗
層領域５をソース領域６に直列に接続することによシ、
ゲインのばらつきを抑制している。しかしながら、ソー
ス領域６の深さ方向の肉厚りが、エピタキシャル層１の
形成の際におけるエピタキシャル層の厚さｆＩＷ、及び
半導体基板２からの高濃度不純物のしみ出しや、ソース
領域６等を形成する際の熱処理によって、大きくばらつ
く。In the semiconductor device 15 configured in this way, by connecting the source resistance layer region 5 to the source region 6 in series,
Variations in gain are suppressed. However, the thickness of the source region 6 in the depth direction affects the epitaxial layer thickness fIW when forming the epitaxial layer 1, the seepage of high concentration impurities from the semiconductor substrate 2, and the formation of the source region 6, etc. It varies greatly depending on the heat treatment used.
その結果、ソース抵抗が不安定になり、信頼性の高い半
導体装Ｍ１５を得ることができない問題があった。As a result, there was a problem that the source resistance became unstable, making it impossible to obtain a highly reliable semiconductor device M15.
品
本発明は、ソース抵抗を安定にして特 らつきを減らし
く更に信頼性の向上を達成した半導体装置を提供するこ
とをその目的とするものである。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device in which source resistance is stabilized, characteristics are reduced, and reliability is improved.
本発明は、ソース取出ｔ＆に抵抗値が１ｏｏΩ乃至ｉｏ
ｏ ＫＱのソース抵抗体を接続して、ソース抵抗を安定
にすることにょシ、特荏肴らつきを減らし更に信頼性の
向上を達成した半導体装置である。The present invention has a resistance value of 1ooΩ to io
This is a semiconductor device that connects a KQ source resistor to stabilize the source resistance, thereby reducing fluctuations and further improving reliability.
以下、本発明の実施例について図面を参照して説明する
。Embodiments of the present invention will be described below with reference to the drawings.
第２図ω乃至同図（ｄは、一実施例の半導体装置の構成
を製造工程に従って示す説５明図である。FIGS. 2(o) to 2(d) are explanatory diagrams showing the structure of a semiconductor device according to an embodiment according to manufacturing steps.
先ず、第２図６）に示す如く、Ｐ導１ｂ、型の半導体基
枡２０上にエピタキシャル成長によＪＮ型のエピタキシ
ャル層２１を形成する。次いで、エピタキシャル層２ノ
に所定パターンの酸化膜を形成して、これをマスクにＰ
導電型の不純物の選択拡散を施し、アイソレーション層
２２によって仕切られた島領域２３を設ける。次に、島
領域２３、アイソレーション層２２を含むエピタキシャ
ル層２ノの主面を覆う酸化膜２４を形成する。First, as shown in FIG. 2, a JN-type epitaxial layer 21 is formed by epitaxial growth on a P-type semiconductor substrate 20. As shown in FIG. Next, an oxide film with a predetermined pattern is formed on the epitaxial layer 2, and P is deposited using this as a mask.
Selective diffusion of conductive type impurities is performed to provide island regions 23 partitioned by isolation layers 22. Next, an oxide film 24 is formed to cover the main surface of the epitaxial layer 2 including the island region 23 and the isolation layer 22.
次に、同図（Ｂ）に示す如く、ダート形成予定領域に対
応して絶縁膜２４に窓２５を開口する。Next, as shown in FIG. 2B, a window 25 is opened in the insulating film 24 corresponding to the area where the dirt is to be formed.
この窓２５を介して島領域２３に接続する多結晶シリコ
ン層を形成する。多結晶シリコン層中には、例えばはロ
ンが含有されている。この不純物の濃度は、後述するソ
ース抵抗体２７の抵抗値が１００Ω乃至１００ ＫＱの
範囲になるように設定する。次いで、多結晶シリコン層
に所定の７４ターニングを施し、島領域２３に接続する
ゲート取出電極２６と、ソース抵抗体２７を絶縁膜２４
上に形成する。この処理の際にゲート取出電極２６の直
下の島領域２３内には、Ｐ型の高濃度不純物領域２８が
形成されている。A polycrystalline silicon layer connected to the island region 23 through this window 25 is formed. The polycrystalline silicon layer contains, for example, ron. The concentration of this impurity is set so that the resistance value of the source resistor 27, which will be described later, is in the range of 100Ω to 100KQ. Next, the polycrystalline silicon layer is subjected to a predetermined 74 turns, and the gate lead-out electrode 26 connected to the island region 23 and the source resistor 27 are connected to the insulating film 24.
Form on top. During this process, a P-type high concentration impurity region 28 is formed in the island region 23 directly under the gate extraction electrode 26.
次に、同図（Ｃ）に示す如く、島領域２３内の絶縁膜２
４の部分に窓２９．３０を開口し、この窓２９．３０を
介してＮ型不純物の選択拡散を行って、島領域２３内に
ソース領域３ノ及びドレイン領域３２を形成する。次い
で、窓２９゜３０を介してソース領域３１及びドレイン
領域３２に接続する電極金私層をゲート取出電極２６、
ソース抵抗体２７を含む絶縁膜２４上に形成する。この
電極金属層にノぐターニングを施してゲート取出電極２
６上にダート電極３３を、ドレイン領域３２上にはドレ
イン取出亀＆３４を、ソース領域３１上には、他端側か
ソース抵抗体２゛７に接続するソース取出配線層３５ｆ
、また、ソース抵抗体２７上にはソース取出電極３６を
形成して半導体装置４０を得る。Next, as shown in FIG.
A window 29.30 is opened in the portion 4, and N-type impurities are selectively diffused through the window 29.30 to form a source region 3 and a drain region 32 in the island region 23. Next, the electrode gold layer connected to the source region 31 and drain region 32 through the window 29°30 is connected to the gate lead electrode 26,
It is formed on the insulating film 24 including the source resistor 27. This electrode metal layer is turned to form a gate lead-out electrode 2.
A dirt electrode 33 is provided on the drain region 32, a drain lead wire layer 35f is provided on the source region 31, and a source lead wiring layer 35f is connected to the other end of the source resistor 2-7.
Further, a source lead-out electrode 36 is formed on the source resistor 27 to obtain a semiconductor device 40.
このように構成された半導体装％４ｏによれば、ソース
抵抗体２７は、エピタキシャル層２１と絶縁＃２４を介
して分離しておシ、しかも、ソース領域３ノ及びドレイ
ン領域３２の形成後に設けられるので、その抵抗値を極
めて安定した値に設定することができる。その結果、ソ
ース抵抗を安定にしてゲインのばらつきを小さくシ、信
頼性の向上を達成することができる。According to the semiconductor device %4o configured in this way, the source resistor 27 is separated from the epitaxial layer 21 via the insulation layer 24, and is provided after the formation of the source region 3 and the drain region 32. Therefore, the resistance value can be set to an extremely stable value. As a result, it is possible to stabilize the source resistance, reduce variation in gain, and improve reliability.
以上説明した如く、本発明に係る半導体装置によれば、
ソース抵抗を安定にして特性ばらつきを減らし、更に信
頼性を向上させることができるものである。As explained above, according to the semiconductor device according to the present invention,
This makes it possible to stabilize the source resistance, reduce characteristic variations, and further improve reliability.
第１図は、従来の半導体装置の概略構成を示す断面図、
第２図（Ａ）乃至同図（Ｃ）は、本発明の実施例の半導
体装置の構成を製造工程順に示す説明図である。
２０・・・半導体基板、２１・・・エピタキシャル層、
２２・・・アイソレーション層、２３・・・島領域、２
４・・・絶縁膜、２５，２９．３０・・・窓、２６・・
・ダートを出電極、２７・・・ソース抵抗体、２８・・
・高濃度不純物領域、３ノ・・・ソース＠城、３２・・
・ドレイン領域、３３・・・ダート％Ｊ、３４・・・ド
レイン取出電極、３５・・・ソース取出前ｆＰ、ｌ＜’
ｍ、ｓ ６・・・ソース取出電極、４０・・・半導体装
１ド。FIG. 1 is a cross-sectional view showing a schematic configuration of a conventional semiconductor device;
FIGS. 2A to 2C are explanatory diagrams showing the structure of a semiconductor device according to an embodiment of the present invention in the order of manufacturing steps. 20... Semiconductor substrate, 21... Epitaxial layer,
22... Isolation layer, 23... Island region, 2
4... Insulating film, 25, 29. 30... Window, 26...
- Dart output electrode, 27... Source resistor, 28...
・High concentration impurity region, 3... Source @ Castle, 32...
・Drain region, 33... Dirt %J, 34... Drain extraction electrode, 35... fP before source extraction, l<'
m, s 6... Source extraction electrode, 40... Semiconductor device 1 drive.
Claims (1)
対導電型のソース領域とドレイン領域と、該ソース領域
及び該ドレイン領域を含む前記半導体基板の主面に形成
された絶縁膜と、該絶縁膜に開口されたコンタクトホー
ルを介シて前記ソース領域に接続するソース取出電極と
、該ソース取出電極に接続し、抵抗値が１００Ω乃至１
００にΩの多結晶シリコンからなるソース抵抗体と、前
記絶縁膜に形成されたコンタクトホールを介して前記半
導体基板のダート領域上に形成された所定の不純物を含
有した多結晶シリコンからなるダート電極とを具備する
ことを特徴とする半導体装置。a source region and a drain region of opposite conductivity type formed at a predetermined distance on a semiconductor substrate of one conductivity type; an insulating film formed on the main surface of the semiconductor substrate including the source region and the drain region; a source extraction electrode connected to the source region through a contact hole opened in an insulating film; and a source extraction electrode connected to the source extraction electrode and having a resistance value of 100Ω to 1.
a source resistor made of polycrystalline silicon with a resistance of 0.00Ω, and a dirt electrode made of polycrystalline silicon containing a predetermined impurity formed on the dirt region of the semiconductor substrate through a contact hole formed in the insulating film. A semiconductor device comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP795684A JPS60152069A (en) | 1984-01-20 | 1984-01-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP795684A JPS60152069A (en) | 1984-01-20 | 1984-01-20 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60152069A true JPS60152069A (en) | 1985-08-10 |
Family
ID=11679938
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP795684A Pending JPS60152069A (en) | 1984-01-20 | 1984-01-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60152069A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5468978A (en) * | 1993-07-07 | 1995-11-21 | Dowben; Peter A. | Forming B1-x Cx semiconductor devices by chemical vapor deposition |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5249777A (en) * | 1975-10-20 | 1977-04-21 | Mitsubishi Electric Corp | Process for production of field effect transistor |
| JPS57114287A (en) * | 1981-01-08 | 1982-07-16 | Toshiba Corp | Semiconductor device |
| JPS5873160A (en) * | 1981-10-26 | 1983-05-02 | Nissan Motor Co Ltd | Input protective device for semiconductor element |
-
1984
- 1984-01-20 JP JP795684A patent/JPS60152069A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5249777A (en) * | 1975-10-20 | 1977-04-21 | Mitsubishi Electric Corp | Process for production of field effect transistor |
| JPS57114287A (en) * | 1981-01-08 | 1982-07-16 | Toshiba Corp | Semiconductor device |
| JPS5873160A (en) * | 1981-10-26 | 1983-05-02 | Nissan Motor Co Ltd | Input protective device for semiconductor element |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5468978A (en) * | 1993-07-07 | 1995-11-21 | Dowben; Peter A. | Forming B1-x Cx semiconductor devices by chemical vapor deposition |
| US5658834A (en) * | 1993-07-07 | 1997-08-19 | Syracuse University | Forming B1-x Cx semiconductor layers by chemical vapor deposition |
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