JPS5889854A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5889854A JPS5889854A JP18803381A JP18803381A JPS5889854A JP S5889854 A JPS5889854 A JP S5889854A JP 18803381 A JP18803381 A JP 18803381A JP 18803381 A JP18803381 A JP 18803381A JP S5889854 A JPS5889854 A JP S5889854A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- capacitor
- insulating film
- oxide film
- polycrystalline silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 4
- 239000003990 capacitor Substances 0.000 claims abstract description 28
- 239000010410 layer Substances 0.000 claims description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 20
- 239000011229 interlayer Substances 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 6
- 235000014121 butter Nutrition 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 230000010354 integration Effects 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 239000002184 metal Substances 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 3
- 239000012535 impurity Substances 0.000 abstract description 2
- 238000007493 shaping process Methods 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はキャパシタを有する半導体装置に於いて、高集
積化を図った構造及び製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a highly integrated structure and manufacturing method of a semiconductor device having a capacitor.
単導体集積回路技術の進歩と共に伝送機器に多くの工０
．Ｌｌｉｉ工がｍｍされるようになりている。With the advancement of single-conductor integrated circuit technology, a lot of work is required for transmission equipment.
．． Llii engineering is now being made into mm.
伝送装置に於いて重要な部品の１つであるフィルタは、
近年のＬ８工技術の進歩により工０化が可能とみり、例
えばスイッチ−とキャパシタを組み合わせたフィルタ、
スイッチトφキャパシタｅフィルタ等もＭＯ８工０によ
り実現できるようになっている。工０に於けるキャパシ
タの構成決め一般的な方法として、２層の多結晶シリコ
ン間にシリコン酸化膜を形成された構造があるが、本発
明では前記の構造で形成されたキャパシタを有する半導
体装置について述べる。A filter is one of the important parts in transmission equipment.
With recent advances in L8 engineering technology, we believe it is possible to reduce the process to 0. For example, filters that combine switches and capacitors,
Switched φ capacitor e-filters and the like can also be realized using MO8-0. A general method for determining the configuration of a capacitor in the process 0 is a structure in which a silicon oxide film is formed between two layers of polycrystalline silicon, but in the present invention, a semiconductor device having a capacitor formed with the above structure is used. Let's talk about.
第１図に従来の構造を示す。FIG. 1 shows a conventional structure.
第１図（蜀では１層目のｎ晶シリコンをキャパシタの下
側電極１０５に用い、゛２層目の多結晶シリコンをゲー
ト電極１０４、キャパシタの上側電極１０８、配＄１１
０６に用いている。高集積化を図るためには配線用の多
結晶シリコンを一２層にすることが考えられる。Figure 1 (In Shu, the first layer of n-crystalline silicon is used for the lower electrode 105 of the capacitor, and the second layer of polycrystalline silicon is used for the gate electrode 104, the upper electrode 108 of the capacitor, and the electrode 11.
Used in 06. In order to achieve high integration, it is conceivable to use 12 layers of polycrystalline silicon for wiring.
第１図（Ｂ）がその１例である。同図（Ｂ）ではキャパ
シタの上側電極２ｃｉｓと共に配線２０９にも２層目の
多結晶シリコ’ｙ、 ＠用いている。こ″のように１−
贋目、２層目多結晶シリ；ンを配線に使用することによ
って従来の第１図（〜の構造よりは高集積化を図ること
ができる。従来の製造方法によれば、キャパシタは１層
目の多結晶シリコン２０５を熱酸化し、その上に２層目
の多結晶シリコン２０８を設けるこ、とにより構成され
ている０例えば２００ＰＦ／−の容量値を得るのに上記
の熱酸化膜２０７は約２ｏｏｏ、Ｘであり、キャパシタ
の面積が決まっていれば、容量値を大きくするには熱酸
化膜厚を薄くするしかない。ところがこの製造方法では
、１層目の多結晶シリコン配線２０６と２層目の多結晶
シリコン配線２０９の間も上記の熱酸化膜２０７である
ために、配線がクロスする領域では配線間に容量をもつ
ため好ましくない。本発明は上記の欠点を改良したもの
である。FIG. 1(B) is one example. In the same figure (B), the second layer of polycrystalline silicon is used for the wiring 209 as well as the upper electrode 2cis of the capacitor. 1- like this
By using the second layer of polycrystalline silicon for wiring, it is possible to achieve higher integration than the conventional structure shown in Figure 1 (~).According to the conventional manufacturing method, the capacitor is made of one The above thermal oxide film 207 is constructed by thermally oxidizing the first polycrystalline silicon 205 and providing a second layer of polycrystalline silicon 208 thereon. is approximately 2ooo, Since the thermal oxide film 207 is also present between the second layer polycrystalline silicon interconnects 209, there is undesirable capacitance between the interconnects in the area where the interconnects cross.The present invention improves the above drawbacks. be.
本発明の目的とするところは、キャパシタの絶縁膜と、
配線間の絶縁膜を別途に形成することにより、キャパシ
タの容量値を保証すると共に配線間の容量をなくシ、キ
ャパシタ形成に用いた２層の多結晶シリコンをそれぞれ
配線に使用して高集積化を図るものである。The object of the present invention is to provide an insulating film of a capacitor;
By separately forming an insulating film between the wiring lines, the capacitance value of the capacitor is guaranteed and the capacitance between the wiring lines is eliminated, and the two layers of polycrystalline silicon used to form the capacitor are used for each wiring line to achieve high integration. The aim is to
以下第２図に従って本発明の１実施例を説明する。An embodiment of the present invention will be described below with reference to FIG.
第２図（、）で、Ｐ型のシリコン基板３０１に機知の方
法でフィールド酸化膜３０２を形成し、その後ゲート酸
化膜３０３を設けた後、１層目の多結晶シリコンを形成
し、ゲート電極３０４、キャパシタの下側電極３０５、
配線３０６を設ける。In FIG. 2(,), a field oxide film 302 is formed on a P-type silicon substrate 301 using a clever method, and then a gate oxide film 303 is formed, and then a first layer of polycrystalline silicon is formed, and a gate electrode is formed. 304, lower electrode 305 of capacitor;
Wiring 306 is provided.
次に同図（ｂ）のように全面にＮ型を有する不純物を拡
散し、ソースドレイン領域３０７を形成、その後ＯＶ’
Ｄ法により層間絶縁膜３０８を形成し、ホトエッチ工程
によりキャパシタ部に窓開けをする。Next, as shown in FIG. 3(b), N-type impurities are diffused over the entire surface to form source/drain regions 307, and then OV'
An interlayer insulating film 308 is formed by method D, and a window is opened in the capacitor portion by a photoetch process.
その後熱酸化により、キャパシタ下側電極３０５に所定
の熱酸化膜３０９を形成し、ソース・ドレイン領域との
コンタクト用の窓開けをしたのが同図（ｃ）である。Thereafter, a predetermined thermal oxide film 309 is formed on the capacitor lower electrode 305 by thermal oxidation, and windows for contact with the source/drain regions are opened, as shown in FIG. 3(c).
次に２層目の多結晶シリコンを設け、ソース番ドレイン
とのコンタクト３１０、キャパシタ部作特性極３１１．
２層目の配線５１２を配線形成する。Next, a second layer of polycrystalline silicon is provided, including contacts 310 with the source and drain, capacitor operation characteristic poles 311 .
A second layer wiring 512 is formed.
さらに層間絶縁膜３１３を設け、ムを等の配線用金属で
配線形成したものが同図（ｄ）である。In addition, an interlayer insulating film 313 is provided, and wiring is formed using a metal for wiring such as silica, as shown in FIG. 4(d).
以上のような製造方法によれば、キャパシタの所定の容
置値を得ると共に、配線用の多結晶シリコン間で容量を
持たないため、キャパシタ形成に用いた２層の多結晶シ
リコンをそのまま２層配線に使用できるため、従来の構
造よりもより高集積化が可能である。このように本発明
は、キヤ、＜シAccording to the manufacturing method described above, a predetermined capacitance value of the capacitor can be obtained, and since there is no capacitance between the polycrystalline silicon for wiring, the two layers of polycrystalline silicon used for forming the capacitor can be directly converted into two layers. Since it can be used for wiring, higher integration is possible than with conventional structures. In this way, the present invention
第１図（Ａ） ｔ （Ｂ）が従来の構造であり、第２図
（ａ）。
（６） ＋ （ｃ） ｓ （ｄ）が本発明による構造、
及び製造方法である。
３０１・・・２Ｍシリコン基板
３０２・・・フィールド酸化膜
３０５・・・ゲート酸化膜
５０４・・・ゲート電極
３０５・・・キャパシタ下側電極
３０６・・・１層多結晶シリコン配線
３０７・・・ソース・ドレイン領域
３０８・・・層間絶縁膜
３０９・・・シリコン酸化膜
３１０・・・ソース・ドレインとのコンタクト用多結晶
シリコン
３１１・・・キャパシタ上側電極
３１２・・・２層目多結晶シリコン配線５１３・・・層
間絶綾膜
３１４・・・配線用金属
以 上Figures 1(A) and 2(B) show the conventional structure, and Figure 2(a) shows the conventional structure. (6) + (c) s (d) is the structure according to the present invention,
and a manufacturing method. 301...2M silicon substrate 302...Field oxide film 305...Gate oxide film 504...Gate electrode 305...Capacitor lower electrode 306...1-layer polycrystalline silicon wiring 307...Source - Drain region 308...Interlayer insulating film 309...Silicon oxide film 310...Polycrystalline silicon 311 for contact with source/drain...Capacitor upper electrode 312...Second layer polycrystalline silicon wiring 513 ...Interlayer twill film 314...More than metal for wiring
Claims (1)
、ホトエッチ工程により該層間絶縁膜に所定のバタ・−
ンに窓開けをする工程と、熟議化によ、り前記１層目多
結晶シリコン上に酸化膜を形成する工程と、その後第２
層目の多結晶シリコンを形成することによって得られる
キャパシタを有することを特徴とする半導体装置。1) After forming an interlayer insulating film on the first layer of polycrystalline silicon, a predetermined amount of butter is applied to the interlayer insulating film by a photoetch process.
a step of opening a window on the first layer, a step of forming an oxide film on the first layer of polycrystalline silicon through deliberation, and then a step of forming a second layer of polycrystalline silicon.
1. A semiconductor device comprising a capacitor obtained by forming multiple layers of polycrystalline silicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18803381A JPS5889854A (en) | 1981-11-24 | 1981-11-24 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18803381A JPS5889854A (en) | 1981-11-24 | 1981-11-24 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5889854A true JPS5889854A (en) | 1983-05-28 |
Family
ID=16216484
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18803381A Pending JPS5889854A (en) | 1981-11-24 | 1981-11-24 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5889854A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6197855A (en) * | 1984-10-18 | 1986-05-16 | Matsushita Electronics Corp | Manufacture of semiconductor device |
| US5030588A (en) * | 1988-04-05 | 1991-07-09 | Seiko Instruments Inc. | Method of making semiconductor device with film resistor |
| US5086370A (en) * | 1990-08-24 | 1992-02-04 | Analog Devices, Incorporated | Integrated circuit chip formed with a capacitor having a low voltage coefficient, and method of making such capacitor |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50159284A (en) * | 1974-06-12 | 1975-12-23 | ||
| JPS5240987A (en) * | 1975-09-29 | 1977-03-30 | Citizen Watch Co Ltd | Integratd capacitance element |
| JPS5693359A (en) * | 1979-12-26 | 1981-07-28 | Mitsubishi Electric Corp | Semiconductor integrated circuit and manufacture |
| JPS57132354A (en) * | 1981-02-09 | 1982-08-16 | Mitsubishi Electric Corp | Semiconductor memory storage |
-
1981
- 1981-11-24 JP JP18803381A patent/JPS5889854A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50159284A (en) * | 1974-06-12 | 1975-12-23 | ||
| JPS5240987A (en) * | 1975-09-29 | 1977-03-30 | Citizen Watch Co Ltd | Integratd capacitance element |
| JPS5693359A (en) * | 1979-12-26 | 1981-07-28 | Mitsubishi Electric Corp | Semiconductor integrated circuit and manufacture |
| JPS57132354A (en) * | 1981-02-09 | 1982-08-16 | Mitsubishi Electric Corp | Semiconductor memory storage |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6197855A (en) * | 1984-10-18 | 1986-05-16 | Matsushita Electronics Corp | Manufacture of semiconductor device |
| US5030588A (en) * | 1988-04-05 | 1991-07-09 | Seiko Instruments Inc. | Method of making semiconductor device with film resistor |
| US5086370A (en) * | 1990-08-24 | 1992-02-04 | Analog Devices, Incorporated | Integrated circuit chip formed with a capacitor having a low voltage coefficient, and method of making such capacitor |
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