JPS5897869A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To inhibit a short-channel effect and a punch-through phenomenon without increasing the resistance of a diffusion layer by diffusing an impurity in shape that diffusion depth is shallow in the vicinity of a channel region and diffusion depth is deep in sections except said region. CONSTITUTION:A polycrystal silicon layer 14 is patterned and a gate electrode 14' is formed, and the unnecessary section of a gate oxide film 13 is removed through etching. Phosphorus is thermally diffused while using a phosphorus added polycrystal silicon layer 15 as a diffusion source through the heat treatment of desirable temperature and time in an oxidizing atmosphere, and n<+> type source region 18 and drain region 19 are shaped. The diffusion constant of phosphorus at a section where the phosphorus added polycrystal silicon layer 15 is protected from the oxidizing atmosphere by a silicon nitride film pattern 16' is made smaller than a section where the diffusion source 15 is exposed directly to the oxidizing atmosphere in thermal diffusion at that time. Accordingly, the stepped source region 18 and drain region 19, diffusion depth thereof is shallow in the vicinity of the channel region and diffusion depth thereof is deep at the outside of the channel region, are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, particularly an insulating dart type electric field, effect semiconductor device. do.

2. Description of the Related Art The recent trend toward miniaturization and higher density of insulating dart type field effect semiconductor devices, typified by MO8 type semiconductor devices, is extremely remarkable. On the other hand, however, with the miniaturization of elements, disadvantageous problems such as short channel effects and 7-mother anti-through have become apparent. The situation during this time can be explained as follows.

First, a conventional manufacturing method of an MO8 type semiconductor device with a miniaturized element will be schematically explained using an n-channel MO8 type semiconductor device as an example.

(1) First, a p-type semiconductor substrate 1 is selectively oxidized to form an element region surrounded by a field oxide film 2. Subsequently, a dirt oxide film 3 is formed on the intended channel region of the element region.
The dirt electrode 4 made of a polycrystalline silicon layer is then turned through the polycrystalline silicon layer (as shown in FIG. 1(, )).

(11) Next, by doping the device region with an n-type impurity such as phosphorus using the f-) electrode 4 as a mask, n-type source and drain regions 5.6 are formed with self-alignment lines (Fig. ).

By using a polycrystalline silicon layer with a high melting point for the dart electrode 4 as described above, the source and drain regions 5 and 6 are
The so-called self-alignment process, which is formed by self-alignment, is
Since there is no need to allow for margins in mask alignment, this method is advantageous for miniaturizing elements, and is generally used as a method for manufacturing MO8 type semiconductor devices with short channel lengths.

By the way, the final V of the source and drain regions 5 and 6
The inner regions 5 and 6 are formed to have a diffusion depth of C0, 5 to 1.5 μm, but since impurity diffusion is dimensional,
Even when formed by self-alignment, they are formed by penetrating under the dart electrode 4 as shown in the figure. As a result, the effective channel length becomes shorter than the designed channel length, resulting in a new short channel effect in which the threshold voltage is lower than a predetermined value. In today's miniaturized devices with channel lengths of 2 μm or less, this channel effect appears prominently, and the threshold voltage varies greatly due to slight dimensional differences in the dart electrodes 4, reducing the reliability of the device. A problem arises in that the value decreases. Furthermore, when the device is miniaturized, the depletion layer formed by the drain region 6 and the depletion layer formed by the source region 5 become connected, and the device becomes conductive even though no voltage is applied to the f-to electrode 4. A new punch-through phenomenon is also likely to occur. If the effective channel length is shortened for the above-mentioned reasons, the knee-through phenomenon becomes even more likely to occur, which becomes an extremely serious problem in terms of device reliability.

The most effective way to simultaneously suppress the short channel effect and the /4' inch-through phenomenon is to reduce the sa6% of the source and drain regions and the diffusion depth of the diffusion layer by making dirt electrodes in the source and drain regions 5.6 The objective is to prevent the effective channel length from shortening by suppressing the downward intrusion. However, if the overall depth of the diffusion layer is made shallow, other problems such as the resistance of the diffusion layer becomes high, the current value necessary for circuit operation cannot be obtained, or the operation speed of the circuit decreases. will occur.

The present invention has been made in view of the above-mentioned circumstances, and provides a method for manufacturing a semiconductor device that can suppress the short channel effect and punch-through phenomenon without causing an increase in the resistance of the diffusion layer.

That is, the present invention includes a step of forming an element region on a semiconductor substrate of a first conductivity type, a step of forming a dart electrode on a portion of the element region where a channel region is to be formed, via a dart insulating film,
By depositing a diffusion source layer containing impurities of the second conductivity type over the entire surface, and depositing a film that suppresses oxygen diffusion over the entire surface and then turning it, it is possible to form a dirt electrode. An oxygen diffusion suppressing film /J? that covers the diffusion source layer near the outside of both ends. and forming a source region and a drain region by thermally diffusing impurities of the second conductivity type from the diffusion source layer by heat treatment in an oxidizing atmosphere. This is a method for manufacturing a semiconductor device.

The present invention focuses on the fact that the thermal diffusion coefficient of impurities in a non-oxidizing ambient atmosphere is smaller than that in an oxidizing atmosphere, and by utilizing this difference in diffusion coefficient, The impurity is diffused with a shallow diffusion depth in the vicinity and a deep diffusion depth in other parts, thereby preventing a reduction in the effective channel length without increasing the resistance of the diffusion layer. Thereby, it is possible to obtain a semiconductor device in which the short channel effect and the knee-through phenomenon are suppressed without sacrificing the operating speed.

As the diffusion source layer in the present invention, a polycrystalline silicon layer doped with impurities, a silicon oxide film, etc. can be used. As the impurity added to this diffusion source layer, an n-type impurity such as phosphorus or arsenic, or a p-type impurity such as zolon can be used.

In addition to the silicon nitride film, alumina film, etc. that are commonly used as oxidation-resistant films, the oxygen diffusion suppression film in the present gAK may be any film that can suppress oxygen diffusion, such as a thick CVD-8102 film. Any material may be used.

An embodiment of the present invention will be described below with reference to FIGS. 2(a,) to (g).

Embodiment (1) First, a field oxide film 12 is formed by selective placement on a p-type -7 silicon substrate 11, and element regions isolated from the field oxide film 12 are formed. Subsequently, the surface of the element region is thermally oxidized to form an f-) oxide film 13, and then a polycrystalline silicon layer 14 is deposited on the entire surface by CVD (as shown in FIG. 1(a)).

(-) Next, the first polycrystalline silicon layer 14 is grain-turned by photolithography to form f-) electrodes 14'. Next, this? -) Unnecessary portions of the dirt oxide film 13 are etched and removed using the electrode 14 as a mask (as shown in Figure Cb).

(+++) Next, after a phosphorous-doped polycrystalline silicon layer 15 having a desired thickness and phosphorus concentration is deposited over the entire surface by CVD, a silicon nitride film 16 is further deposited thereon. Subsequently, 7 photoresist (for example, 0FPR-800 manufactured by Tokyo Applied Chemical Co., Ltd.) is coated on the entire surface, and exposed and exposed to form a resist that locally covers the silicon nitride film 16 at the dirt electrode 14' and its vicinity. A straight turn 17 is formed (as shown in FIG. 3(c)).

(lv) Next, using the resist/arm turf 17 as a mask, the silicon nitride film 16 is turned by a certain amount by using a mixed gas of CF4 + H2 or by active ion etching, and phosphorus is locally added to the dirt electrode 14 and its vicinity. A silicon nitride film pattern 16' is formed to cover the polycrystalline silicon layer 15 (as shown in FIG. 4D).

(Next, by performing heat treatment in an oxidizing atmosphere at a desired temperature and time, phosphorus is thermally diffused using the phosphorus-doped polycrystalline silicon layer 15 as a diffusion source, and the source region 18 and drain region of the mold are 19 (see figure (
,) as shown).

During thermal diffusion at this time, the phosphorous-doped polycrystalline silicon layer 1
In the portion where the diffusion source 15 is protected from the oxidizing atmosphere by the silicon nitride film arm turn 16', the diffusion coefficient of phosphorus is smaller than in the portion where the diffusion source 15 is directly exposed to the oxidizing atmosphere. Therefore, as shown in the figure, a stepped source region 18 and a drain region 19 are formed with a shallow diffusion depth near the channel region and a deep diffusion depth outside the channel region.

(■1) Next, the remaining silicon nitride film pattern 16'
Then, the phosphorus-doped polycrystalline silica layer 15 is removed by etching (as shown in FIG. 3(f)).

(V+O Next, CVD -5t on the entire surface as an interlayer insulating film.
After depositing the O□ film 20, a contact hole is opened,
Subsequently, sia aluminum wirings 21 and 21 are formed by vapor deposition of aluminum 8 and /l turning (see (g) in the same figure).
).

According to the manufacturing method of the above embodiment, the portion of the source and drain region 1 g e J 9 near the channel region can be formed with a shallow diffusion depth, so that the short channel effect and punch-through phenomenon due to the reduction in the effective channel length can be prevented. Therefore, a highly reliable MDS type semiconductor device can be manufactured. at the same time,
Since the source and drain regions 1g, xy portions other than the vicinity of the channel region, and other diffusion layers are formed with a deep diffusion depth, the resistance of the diffusion layers can be made sufficiently low.

Therefore, unlike the case where the entire diffusion layer is formed shallowly, the operation speed is not delayed due to increased resistance.

Furthermore, when a polycrystalline silicon layer is used for the r-) electrode 14', it is common practice to dope the polycrystalline silicon layer by thermal diffusion and ion implantation in order to reduce the wiring resistance. According to the method, impurity doping into the Ke-) electrode can be performed simultaneously with the formation of the source and drain 111.19.

In addition, when it is desired to diffuse impurities into the r-) electrode 14' in an oxidizing atmosphere, as shown in FIG. A silicon nitride film/mother turn 16N covering the crystalline silicon layer 15 may be formed.

The present invention also provides a p-channel MO8 type semiconductor device,
It can be applied to the manufacture of all other insulated f-) type semiconductor devices.

As detailed above, the original F! According to AK, short channel effects and 9.
Accordingly, it is possible to provide a method for manufacturing a semiconductor device that can suppress the chip-through phenomenon.

[Brief explanation of the drawing]

Figures 1 (a) and (b) are cross-sectional views showing the main parts in the manufacturing process of a conventional MO8 type semiconductor device, and Figure 2 6)-j
) is a cross-sectional view showing the manufacturing process of one embodiment of the present invention [4-
FIG. 3 is a sectional view for explaining another embodiment of the present invention. DESCRIPTION OF SYMBOLS 11... P-type silicon substrate, 12... Field oxide film, lj... ff-) oxide film, 14... Polycrystalline silicon layer, 14'... f-) electrode, 15... Phosphorus-doped polycrystalline silicon layer, 16... silicon nitride m, 16'
e16N... cy y Q conversion JIL' turn, 17.
...resis)/arm)-n, 1g...source area JLxy
...Drain region, J0-CVD-810□ film,
jM-full<=tsu・4, wiring. Figure 1 Figure 2

Claims (2)

[Claims] (1) A step of forming an element region on a semiconductor substrate of a first conductivity type, and forming an r-
) a step of forming a dirt electrode through an insulating film; a step of depositing a diffusion source layer containing a second conductivity type impurity over the entire surface;
A step of forming an oxygen diffusion suppressing film/main turn covering the diffusion source layer near the outside of both ends of the dirt electrode by depositing a film that suppresses oxygen diffusion over the entire surface and patterning it. and a step of thermally diffusing second conductivity type impurities from the diffusion source layer by heat treatment in an oxidizing atmosphere to form a source region and a drain region. . (2) The semiconductor device according to claim (1), wherein the oxygen diffusion suppressing film pattern is turned by a certain amount so as to cover the diffusion source layer also in the e-) electrode portion. manufacturing method.