JPS60164336A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60164336A JPS60164336A JP1963584A JP1963584A JPS60164336A JP S60164336 A JPS60164336 A JP S60164336A JP 1963584 A JP1963584 A JP 1963584A JP 1963584 A JP1963584 A JP 1963584A JP S60164336 A JPS60164336 A JP S60164336A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- semiconductor
- type
- grown
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
Abstract
Description
【発明の詳細な説明】
〔発明の属ノーる技術分計〕
本発明は半導体装置の酸化膜絶縁分離法または部分酸化
膜絶縁分離法に関し、特に半導体基板上に高さの違った
複数の平面を作シ、この平面の上にエピタキシャル部を
成長させ、その表(3)の一部を部分的に酸化すること
によシ半導体装傷、を形成する半導体装置のJ使造方法
に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical summary to which the invention pertains] The present invention relates to an oxide film insulation isolation method or a partial oxide film insulation isolation method for semiconductor devices, and particularly relates to an oxide film insulation isolation method or a partial oxide film insulation isolation method for semiconductor devices, and in particular, to This invention relates to a method for using a semiconductor device in which a semiconductor chip is formed by growing an epitaxial part on this plane and partially oxidizing a part of the surface (3) of the epitaxial part.
従来、バイポーラ型手導体装渥の送気約分#2法として
、平坦な半導体基板上に埋込層を拡散しそノ後工1−’
タキシャル層を形成し、選択的にこのエピタキシャル部
一部5を酸化する、酸化膜絶縁分離法または部分埼化膜
絶縁分1嘘法が用いられていた。Conventionally, as the air supply reduction method #2 for bipolar type hand conductor devices, a buried layer is diffused on a flat semiconductor substrate and the subsequent process 1-'
An oxide film insulation isolation method or a partial nitride film insulation isolation method has been used in which a taxial layer is formed and a portion 5 of the epitaxial portion is selectively oxidized.
第1図は、従来法の厚い酸化膜を二回成長させること(
今後、二回清化法と呼ぶ)による酸化膜?縁分離法でバ
イポーラ型トランジスタを形成する15合の工種を曖明
するための断面図でるる。Figure 1 shows the conventional method of growing a thick oxide film twice (
An oxide film created by the method (hereinafter referred to as the double-purification method)? This is a cross-sectional view to clarify the type of process used to form a bipolar transistor using the edge separation method.
第1区(a)で、P型半導体基板1にN+型哩込層2
t 拡散L 、 P+軌チャンネルストッパー3を拡散
する。そして、N型エピタキシャルI?F4kMfkさ
せ、薄い徹化膜5及び、窒化膜6を形成し、写* i
i11技術によって、図のように窓を空ける。その後、
算1図(b)の棟に、加圧酸化法などにより、第1回目
の厚い112化膜7を形成する。そして、第1図(C)
に示す様に、この厚い酸化膜7および薄い酸化膜5及び
声化膜6をエツチングし、必要なら再度、薄い酸化膜5
′及び窒化膜6′を着けなおす。さらに、加圧酸化によ
シ第2回目の厚い酸化膜7′を着ける(第1図(d))
。この墳化膜は、半導体装置の電気的分離用の絶厩膜と
なる。次に、第1−ff1(e)の名“に示すコレクタ
の電気的抵抗低減のためのN+型拡散領域を形成し、熱
酸化膜9を成長させ、10のP型ベース頭載を拡散する
。次に。In the first section (a), an N+ type folding layer 2 is formed on a P type semiconductor substrate 1.
t Diffuse L, P+ trajectory channel stopper 3. And N-type epitaxial I? F4kMfk was used to form a thin permeable film 5 and a nitride film 6, and then
Using i11 technology, a window is opened as shown in the figure. after that,
A first thick 112 film 7 is formed on the ridge of Figure 1(b) by a pressure oxidation method or the like. And Figure 1 (C)
As shown in , the thick oxide film 7, the thin oxide film 5, and the voicing film 6 are etched, and if necessary, the thin oxide film 5 is etched again.
' and the nitride film 6' are reattached. Furthermore, a second thick oxide film 7' is formed by pressure oxidation (Fig. 1(d)).
. This embedding film becomes an insulating film for electrical isolation of a semiconductor device. Next, an N+ type diffusion region for reducing the electrical resistance of the collector shown in 1-ff1(e) is formed, a thermal oxide film 9 is grown, and the P type base head of 10 is diffused. .next.
第1図(f)の様に、N 型エミッタ拡散領域12を作
シ、金属電極配線13を作れば、バイポーラ塁トランジ
スタが完成する。As shown in FIG. 1(f), by forming an N type emitter diffusion region 12 and forming a metal electrode wiring 13, a bipolar base transistor is completed.
第1図の方法は1%電気的離用の厚い酸化膜を形成する
際、2回、厚い酸化膜を成長させている。In the method shown in FIG. 1, when forming a thick oxide film with an electrical separation of 1%, the thick oxide film is grown twice.
従ちて、語1図(b)の婢1回目の酸化時に、半導体が
酸化膜に変る際に半導体は膨張するので、酸化膜とエピ
タキシャル層の界面に近い領域にストレスが溜る。そし
て、第1図(d)の2度目の酢化の際にも、酸化膜とエ
ピタキシャル層の界面に近い領域に、更にストレスが蓄
えられる。こうしてできたトランジスタのベースとコレ
クタの耐圧〔以下BVcboと呼ぶ〕は、この2回もの
酸化によるストレス泌加わるiとで発生した結晶欠陥の
ため、低くなってしまう欠点を持っていた。Therefore, during the first oxidation shown in FIG. 1(b), the semiconductor expands when it changes into an oxide film, and stress accumulates in the region near the interface between the oxide film and the epitaxial layer. During the second acetylation as shown in FIG. 1(d), stress is further accumulated in the region near the interface between the oxide film and the epitaxial layer. The breakdown voltage of the base and collector (hereinafter referred to as BVcbo) of the transistor thus formed had the disadvantage of being low due to crystal defects generated by the addition of stress caused by these two oxidations.
本発明の目的は、半導体装置の酸化膜絶椰1分離法″−
1光は部分酸化膜絶縁分業法で、寺に二回言化法による
絶縁分離法において、酸化膜と半導体の界面に近い領域
に蓄えられるストレスを低減し、BVcboの高い半導
体装置を作る方法を提供することにある。The purpose of the present invention is to provide a method for separating oxide films in semiconductor devices.
1 Hikari is a partial oxide film insulation division method, and in the dielectric isolation method using the double oxidation method, we have developed a method to reduce the stress accumulated in the region near the interface between the oxide film and the semiconductor, and to create semiconductor devices with high BVcbo. It is about providing.
本発明の半導体装置の製造方法は、半導体基板上に第1
の半導体層を成長させ、その一部を酸化やエツチングに
より、半導体基板上に高さの違った複数の平面を作シ、
第2の半導体層を成長させ。In the method for manufacturing a semiconductor device of the present invention, a first
By growing a semiconductor layer and oxidizing or etching a portion of it, multiple planes with different heights are created on the semiconductor substrate.
growing a second semiconductor layer;
その後再び、半導体表面の一部を酸化させ半導体装置の
電気的分離をする半導体装置の製造方法である。Thereafter, a part of the semiconductor surface is oxidized again to electrically isolate the semiconductor device.
次に2本発明の半導体装置の2に遣方法を一実施例を用
いて説明する。Next, a second method of supplying the semiconductor device of the present invention will be explained using an example.
第2図は本発明の半導体装置の二回酸化法による酸化膜
絶縁分離法を説明するための断面図である。第2図(a
)に示す様に、PM半導体基板101にN 型埋込層及
び、P 型チャンネルストッパー103を拡散し、最終
的に必秋なエピタキシャル層の厚さのおよそ半分の厚さ
のNmエピタキシャルr@104を成長する。そして、
薄い酸化膜105及び窒化M106を成長させ、浮具蝕
刻技術により、窓を空ける。その後、第2図(b)のよ
うに、加圧酸化法などによシ 1. i回目の厚い酸化
膜107を形成する。次に、この厚い酸化膜と半導体表
面の薄い酸化膜105と窒化膜106をエツチングによ
シ、除去すると第21MI(C)になる。その後%第2
図(〔すのように、引り最終的な所望の厚さとなるまで
工yタキシャル層104′を成長する。図で破線(7り
は、第1 ri6目のエピタキシャル層の表面の位シを
示すものである。そし1.第2図(e)のように、再び
薄い酸化a:tos’と窒化膜106′を成長させ、第
2回目の絶縁分離用の厚い醸化膜107′を成長、させ
る(第2図(f)入。、さらに、第2図(g)で示すコ
レクタの抵抗仮植用のN 型拡散層108を形成し、1
10で示すP型ベース印智を拡散し、第2図(lりのよ
うに、N 型エミッタ領1虚112を拡セする。最後に
霜極宅シ出し用の金属配線113を蒸着すれは、本発明
の製゛左方法を用いて、バイポーラ型トランジスタを作
ることができる(紀2し[(h))。FIG. 2 is a cross-sectional view for explaining an oxide film insulation isolation method using a double oxidation method for a semiconductor device according to the present invention. Figure 2 (a
), an N-type buried layer and a P-type channel stopper 103 are diffused into a PM semiconductor substrate 101, and finally an Nm epitaxial layer r@104 with a thickness of about half the thickness of the inevitable epitaxial layer is formed. grow. and,
A thin oxide film 105 and M nitride film 106 are grown, and a window is formed using a float etching technique. Thereafter, as shown in FIG. 2(b), oxidation using a pressure oxidation method, etc. 1. The i-th thick oxide film 107 is formed. Next, this thick oxide film and the thin oxide film 105 and nitride film 106 on the semiconductor surface are removed by etching to form the 21st MI (C). then %2nd
As shown in the figure, the epitaxial layer 104' is grown until it reaches the final desired thickness. 1. As shown in Fig. 2(e), a thin oxide a:tos' and nitride film 106' is grown again, and a second thick insulating film 107' is grown. , (see FIG. 2(f)).Furthermore, an N-type diffusion layer 108 for temporary resistor implantation of the collector shown in FIG. 2(g) is formed.
Diffuse the P type base plate shown in 10 and expand the N type emitter region 1 imaginary 112 as shown in Figure 2.Finally, metal wiring 113 for exposing the frost pole is evaporated. By using the manufacturing method of the present invention, a bipolar transistor can be manufactured (Section 2 [(h)).
このようンこして作ったトランジスタでは、穿、i回目
に形成した暉い酸化;漠によるストレスウ;、第2図(
C)のエピタキシャル層内の領域に溜るが、その後り第
2図(d)て示すように、男゛度エビクキシャル層tf
tQ長するのて、新しく成長)−7だエピタキシャル層
には、ストレスの影ψpま無くなる。イアって、第2回
目の酸化膜成長の時には、この時のストレスしか加わら
ないので、酸化膜とエピタキシャル層の界面に発生ずゐ
結晶欠陥は、大幅に抑えることができる。その結果、ト
ランジスタのBVch□ i@圧を大幅に向上させるこ
とができる。In the transistor made in this way, the stress caused by the deep oxidation formed the i-th time;
C), but as shown in FIG. 2(d), the epitaxial layer tf
As the length of tQ increases, the effect of stress ψp disappears on the newly grown epitaxial layer (-7). During the second oxide film growth, only the stress at this time is applied, so crystal defects can be significantly suppressed without occurring at the interface between the oxide film and the epitaxial layer. As a result, the BVch□i@ pressure of the transistor can be significantly improved.
以上説明したように、本発明の半導体装置の製造方法を
用いれば、二回酸化法による酸化膜絶縁分離法または部
分酸化膜絶縁分離法を用いた半導体装置の耐圧を大幅に
向上させることができる。As explained above, by using the method for manufacturing a semiconductor device of the present invention, it is possible to significantly improve the breakdown voltage of a semiconductor device using an oxide film isolation method using a double oxidation method or a partial oxide film isolation method. .
第1図は、従来法の二回酸化法を用いた酸化膜絶縁分離
法によるバイポーラ型半導体装置の製造方法を示すだめ
の断面図である。
第2図は1本発明の一実施例による二回酸化法を用いた
酸化膜絶縁分離法によるバイポーラ型半導体装置の製造
方法を説明するための断面図である。
1.101・・・・・・P型半導体基板、2,102・
・・・・・N 型埋込層、3,103・・・・・・P
型チャンネルストッパー、4,104,104’・・・
・・・N型エピタキシャル層、5.5’、105,10
5’・・・・・・薄い酸化膜、 6. 6’、106.
106’・・・・・・窒化膜。
7.7’、107,107’・・・・・・厚い酸化膜、
8゜108・・・・・・N 型コレクタ拡散層、9,1
09°・。
酸化膜、10,110・・・・・・P型ベース領域、1
1゜111・・・・・・酸化膜、12,112・川・・
N 型エミレタ領域、13,113・・・・・・電極域
シ出し用金属配線、(A)・・・・・・第1回目と第2
回目のエピタキシャル層の界面。
第2図FIG. 1 is a cross-sectional view showing a method of manufacturing a bipolar semiconductor device by an oxide film insulation isolation method using a conventional double oxidation method. FIG. 2 is a sectional view for explaining a method of manufacturing a bipolar semiconductor device by an oxide film insulation isolation method using a double oxidation method according to an embodiment of the present invention. 1.101...P-type semiconductor substrate, 2,102.
...N type buried layer, 3,103...P
Type channel stopper, 4,104,104'...
...N-type epitaxial layer, 5.5', 105,10
5'...Thin oxide film, 6. 6', 106.
106'...Nitride film. 7.7', 107, 107'...Thick oxide film,
8゜108...N type collector diffusion layer, 9,1
09°・. Oxide film, 10, 110...P type base region, 1
1゜111...Oxide film, 12,112・River...
N type emitter region, 13, 113...Metal wiring for exposing electrode area, (A)...First and second
The interface of the second epitaxial layer. Figure 2
Claims (1)
導電型の第1の半導体層を成長させ、該第1の半導体層
の一部の厚さを薄くすることによって、牛コ!体基板上
に高さの違った複数の平面を設け11、該第1の半導体
層上に第1導可1型又は第2導電型の第2の半導体層を
設け、該第2の半導体層の一部に鼠化陵を設けることを
特徴とする半導体装置の製造方法。The first conductivity type or the second conductivity type is formed on the semiconductor substrate shouldering the stripe 14 conductivity type.
By growing a first semiconductor layer of a conductive type and reducing the thickness of a portion of the first semiconductor layer, the cow! A plurality of planes having different heights are provided on the body substrate 11, a second semiconductor layer of a first conductivity type or a second conductivity type is provided on the first semiconductor layer, and the second semiconductor layer is provided with a first conductivity type or a second conductivity type. 1. A method for manufacturing a semiconductor device, characterized in that a rat ridge is provided in a part of the semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1963584A JPS60164336A (en) | 1984-02-06 | 1984-02-06 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1963584A JPS60164336A (en) | 1984-02-06 | 1984-02-06 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60164336A true JPS60164336A (en) | 1985-08-27 |
Family
ID=12004666
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1963584A Pending JPS60164336A (en) | 1984-02-06 | 1984-02-06 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60164336A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62208670A (en) * | 1986-03-07 | 1987-09-12 | Toshiba Corp | Manufacture of semiconductor device |
US5382534A (en) * | 1994-06-06 | 1995-01-17 | United Microelectronics Corporation | Field effect transistor with recessed buried source and drain regions |
-
1984
- 1984-02-06 JP JP1963584A patent/JPS60164336A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62208670A (en) * | 1986-03-07 | 1987-09-12 | Toshiba Corp | Manufacture of semiconductor device |
US5382534A (en) * | 1994-06-06 | 1995-01-17 | United Microelectronics Corporation | Field effect transistor with recessed buried source and drain regions |
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